{"id":"https://openalex.org/W4413096106","doi":"https://doi.org/10.1109/smacd65553.2025.11092233","title":"SystemVerilog-Based Modeling and Verification of 25.6-GBaud/Lane PAM-3 Receiver","display_name":"SystemVerilog-Based Modeling and Verification of 25.6-GBaud/Lane PAM-3 Receiver","publication_year":2025,"publication_date":"2025-07-07","ids":{"openalex":"https://openalex.org/W4413096106","doi":"https://doi.org/10.1109/smacd65553.2025.11092233"},"language":"en","primary_location":{"id":"doi:10.1109/smacd65553.2025.11092233","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd65553.2025.11092233","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5119265284","display_name":"Chae-Hyeon Lim","orcid":null},"institutions":[{"id":"https://openalex.org/I161024014","display_name":"Kwangwoon University","ror":"https://ror.org/02e9zc863","country_code":"KR","type":"education","lineage":["https://openalex.org/I161024014"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Chae-Hyeon Lim","raw_affiliation_strings":["Kwangwoon University,Department of Electronics and Communications Engineering,Seoul,Republic of Korea"],"affiliations":[{"raw_affiliation_string":"Kwangwoon University,Department of Electronics and Communications Engineering,Seoul,Republic of Korea","institution_ids":["https://openalex.org/I161024014"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109187956","display_name":"J.H. Yun","orcid":null},"institutions":[{"id":"https://openalex.org/I161024014","display_name":"Kwangwoon University","ror":"https://ror.org/02e9zc863","country_code":"KR","type":"education","lineage":["https://openalex.org/I161024014"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Ju-Hyeong Yun","raw_affiliation_strings":["Kwangwoon University,Department of Electronics and Communications Engineering,Seoul,Republic of Korea"],"affiliations":[{"raw_affiliation_string":"Kwangwoon University,Department of Electronics and Communications Engineering,Seoul,Republic of Korea","institution_ids":["https://openalex.org/I161024014"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113648409","display_name":"Yong-Gyu Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I161024014","display_name":"Kwangwoon University","ror":"https://ror.org/02e9zc863","country_code":"KR","type":"education","lineage":["https://openalex.org/I161024014"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Yong-Gyu Yu","raw_affiliation_strings":["Kwangwoon University,Department of Electronics and Communications Engineering,Seoul,Republic of Korea"],"affiliations":[{"raw_affiliation_string":"Kwangwoon University,Department of Electronics and Communications Engineering,Seoul,Republic of Korea","institution_ids":["https://openalex.org/I161024014"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045809760","display_name":"Joo\u2010Hyung Chae","orcid":"https://orcid.org/0000-0001-6354-5612"},"institutions":[{"id":"https://openalex.org/I161024014","display_name":"Kwangwoon University","ror":"https://ror.org/02e9zc863","country_code":"KR","type":"education","lineage":["https://openalex.org/I161024014"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Joo-Hyung Chae","raw_affiliation_strings":["Kwangwoon University,Department of Electronics and Communications Engineering,Seoul,Republic of Korea"],"affiliations":[{"raw_affiliation_string":"Kwangwoon University,Department of Electronics and Communications Engineering,Seoul,Republic of Korea","institution_ids":["https://openalex.org/I161024014"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5119265284"],"corresponding_institution_ids":["https://openalex.org/I161024014"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.23139649,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11248","display_name":"Advanced Power Amplifier Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.718401312828064}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.718401312828064}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/smacd65553.2025.11092233","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd65553.2025.11092233","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320322120","display_name":"National Research Foundation of Korea","ror":"https://ror.org/013aysd81"},{"id":"https://openalex.org/F4320322202","display_name":"IC Design Education Center","ror":"https://ror.org/005v57z85"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2144962250","https://openalex.org/W2972221098","https://openalex.org/W3023906650","https://openalex.org/W4312420650","https://openalex.org/W4320712953","https://openalex.org/W4396594897"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W4391913857","https://openalex.org/W2358668433","https://openalex.org/W4396701345","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W4396696052"],"abstract_inverted_index":{"We":[0],"present":[1],"a":[2,10,28,34,46,61,64,86],"SystemVerilog-based":[3],"receiver":[4],"(RX)":[5],"modeling":[6,76],"and":[7,33,39,41,50,63],"verification":[8],"for":[9],"universal":[11],"serial":[12],"bus":[13],"4.0":[14],"generation":[15],"4":[16],"(USB4.0":[17],"Gen4).":[18],"In":[19],"the":[20,43,57,72,81],"data":[21,51,87],"path,":[22,45],"analog":[23],"functional":[24],"circuits":[25],"such":[26],"as":[27],"continuous":[29],"time":[30],"linear":[31],"equalizer":[32],"4-input":[35],"comparator":[36],"were":[37,67],"modeled":[38,54,69],"verified,":[40],"in":[42],"clock":[44,49],"2X":[47],"oversampling":[48],"recovery":[52],"was":[53,77],"to":[55,70,79],"validate":[56],"overall":[58],"operation.":[59],"Additionally,":[60],"deserializer":[62],"logical":[65],"layer":[66],"also":[68],"complete":[71],"entire":[73],"RX.":[74],"SystemVerilog":[75],"used":[78],"verify":[80],"USB4.0":[82],"Gen4":[83],"RX":[84],"with":[85],"rate":[88],"of":[89],"25.6":[90],"GBaud/lane.":[91]},"counts_by_year":[],"updated_date":"2025-12-22T23:10:17.713674","created_date":"2025-10-10T00:00:00"}