{"id":"https://openalex.org/W4404239407","doi":"https://doi.org/10.1109/smacd61181.2024.10745390","title":"Set the Clock: A Synthesizable Clock Manager","display_name":"Set the Clock: A Synthesizable Clock Manager","publication_year":2024,"publication_date":"2024-07-02","ids":{"openalex":"https://openalex.org/W4404239407","doi":"https://doi.org/10.1109/smacd61181.2024.10745390"},"language":"en","primary_location":{"id":"doi:10.1109/smacd61181.2024.10745390","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/smacd61181.2024.10745390","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5092779836","display_name":"Jonas Lienke","orcid":null},"institutions":[{"id":"https://openalex.org/I4210145956","display_name":"Institut f\u00fcr Mikroelektronik- und Mechatronik-Systeme","ror":"https://ror.org/0445d9h15","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210145956"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Jonas Lienke","raw_affiliation_strings":["IMMS Institut f&#x00FC;r Mikroelektronik- und Mechatronik-Systeme gemeinn&#x00FC;tzige GmbH (IMMS GmbH),Ilmenau,Germany"],"affiliations":[{"raw_affiliation_string":"IMMS Institut f&#x00FC;r Mikroelektronik- und Mechatronik-Systeme gemeinn&#x00FC;tzige GmbH (IMMS GmbH),Ilmenau,Germany","institution_ids":["https://openalex.org/I4210145956"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069754469","display_name":"Florian K\u00f6gler","orcid":null},"institutions":[{"id":"https://openalex.org/I4210145956","display_name":"Institut f\u00fcr Mikroelektronik- und Mechatronik-Systeme","ror":"https://ror.org/0445d9h15","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210145956"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Florian K\u00f6gler","raw_affiliation_strings":["IMMS Institut f&#x00FC;r Mikroelektronik- und Mechatronik-Systeme gemeinn&#x00FC;tzige GmbH (IMMS GmbH),Ilmenau,Germany"],"affiliations":[{"raw_affiliation_string":"IMMS Institut f&#x00FC;r Mikroelektronik- und Mechatronik-Systeme gemeinn&#x00FC;tzige GmbH (IMMS GmbH),Ilmenau,Germany","institution_ids":["https://openalex.org/I4210145956"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112869791","display_name":"Eric Sch\u00e4fer","orcid":null},"institutions":[{"id":"https://openalex.org/I4210145956","display_name":"Institut f\u00fcr Mikroelektronik- und Mechatronik-Systeme","ror":"https://ror.org/0445d9h15","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210145956"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Eric Sch\u00e4fer","raw_affiliation_strings":["IMMS Institut f&#x00FC;r Mikroelektronik- und Mechatronik-Systeme gemeinn&#x00FC;tzige GmbH (IMMS GmbH),Ilmenau,Germany"],"affiliations":[{"raw_affiliation_string":"IMMS Institut f&#x00FC;r Mikroelektronik- und Mechatronik-Systeme gemeinn&#x00FC;tzige GmbH (IMMS GmbH),Ilmenau,Germany","institution_ids":["https://openalex.org/I4210145956"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102897374","display_name":"Georg Gl\u00e4ser","orcid":"https://orcid.org/0000-0002-7923-0284"},"institutions":[{"id":"https://openalex.org/I4210145956","display_name":"Institut f\u00fcr Mikroelektronik- und Mechatronik-Systeme","ror":"https://ror.org/0445d9h15","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210145956"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Georg Gl\u00e4ser","raw_affiliation_strings":["IMMS Institut f&#x00FC;r Mikroelektronik- und Mechatronik-Systeme gemeinn&#x00FC;tzige GmbH (IMMS GmbH),Ilmenau,Germany"],"affiliations":[{"raw_affiliation_string":"IMMS Institut f&#x00FC;r Mikroelektronik- und Mechatronik-Systeme gemeinn&#x00FC;tzige GmbH (IMMS GmbH),Ilmenau,Germany","institution_ids":["https://openalex.org/I4210145956"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5092779836"],"corresponding_institution_ids":["https://openalex.org/I4210145956"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21805183,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.8220999836921692,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.8220999836921692,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.7638999819755554,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.6751999855041504,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7201371192932129},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6610962152481079},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.6477100849151611},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.5456722974777222},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.5200676321983337},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4596715569496155},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.41988998651504517},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40567636489868164},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3788248300552368},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.34226492047309875},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2264518141746521},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.12231019139289856},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10546353459358215},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.09695833921432495}],"concepts":[{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7201371192932129},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6610962152481079},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.6477100849151611},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.5456722974777222},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.5200676321983337},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4596715569496155},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.41988998651504517},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40567636489868164},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3788248300552368},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.34226492047309875},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2264518141746521},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.12231019139289856},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10546353459358215},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.09695833921432495}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/smacd61181.2024.10745390","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/smacd61181.2024.10745390","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320311649","display_name":"Ministry of Education","ror":"https://ror.org/036nq5137"},{"id":"https://openalex.org/F4320322835","display_name":"Ministry of Economic Affairs","ror":"https://ror.org/042ge0913"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2108458508","https://openalex.org/W2113319198","https://openalex.org/W2900351547","https://openalex.org/W4385412006","https://openalex.org/W6802994847"],"related_works":["https://openalex.org/W3006003651","https://openalex.org/W2088914741","https://openalex.org/W2174922170","https://openalex.org/W2040807843","https://openalex.org/W4247180033","https://openalex.org/W2133326759","https://openalex.org/W4247089581","https://openalex.org/W1525888526","https://openalex.org/W4249038728","https://openalex.org/W2559451387"],"abstract_inverted_index":{"The":[0,96],"design":[1,15],"of":[2,27,117,124,130],"clock":[3,30,37,116,123],"management":[4],"circuitry":[5],"is":[6,51,59,98],"currently":[7],"done":[8],"using":[9,83,107],"a":[10,18,24,28,36,40,45,84,101,115,121,128],"more":[11],"or":[12],"less":[13],"analog":[14,71],"flow.":[16],"For":[17],"current":[19],"chip":[20],"design,":[21],"we":[22],"show":[23],"fully-digital":[25],"implementation":[26],"digital":[29,86],"manager":[31],"(DCM)":[32],"block":[33],"that":[34],"generates":[35],"signal":[38],"from":[39,93,120],"reference":[41,122],"clock.":[42],"It":[43],"utilizes":[44],"PLL-like":[46],"structure":[47],"for":[48,69],"self-calibration":[49],"and":[50,73,77],"implemented":[52,99],"purely":[53],"in":[54,62,100],"Verilog.":[55],"Since":[56],"the":[57,67,94],"DCM":[58,97],"designed":[60],"only":[61],"synthesizable":[63],"Verilog,":[64],"it":[65,113],"eliminates":[66],"need":[68],"an":[70],"simulation":[72,87],"enabling":[74],"automated":[75],"synthesis":[76],"layout.":[78,95],"We":[79],"verify":[80],"our":[81,111],"circuit":[82],"standard":[85],"method":[88],"with":[89,127],"annotated":[90],"timings":[91],"extracted":[92],"commercial":[102],"350":[103],"nm":[104],"CMOS":[105],"technology":[106],"$0.138":[108],"\\mathrm{~mm}^{2}$.":[109],"In":[110],"scenario,":[112],"creates":[114],"70":[118],"MHz":[119,126],"5":[125],"jitter":[129],"30":[131],"ps.":[132]},"counts_by_year":[],"updated_date":"2025-12-22T23:10:17.713674","created_date":"2025-10-10T00:00:00"}
