{"id":"https://openalex.org/W4385411999","doi":"https://doi.org/10.1109/smacd58065.2023.10192216","title":"NVSystolic: Heterogeneous Simulation Framework for Emerging Memories with Systolic Array","display_name":"NVSystolic: Heterogeneous Simulation Framework for Emerging Memories with Systolic Array","publication_year":2023,"publication_date":"2023-07-03","ids":{"openalex":"https://openalex.org/W4385411999","doi":"https://doi.org/10.1109/smacd58065.2023.10192216"},"language":"en","primary_location":{"id":"doi:10.1109/smacd58065.2023.10192216","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/smacd58065.2023.10192216","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5092779819","display_name":"J Chithambara Moorthii","orcid":null},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"J Chithambara Moorthii","raw_affiliation_strings":["Indian Institute of Technology Delhi,New Delhi,India","Indian Institute of Technology Delhi, New Delhi, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Delhi,New Delhi,India","institution_ids":["https://openalex.org/I68891433"]},{"raw_affiliation_string":"Indian Institute of Technology Delhi, New Delhi, India","institution_ids":["https://openalex.org/I68891433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5092779820","display_name":"Sufyan Khanv","orcid":null},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sufyan Khanv","raw_affiliation_strings":["Indian Institute of Technology Delhi,New Delhi,India","Indian Institute of Technology Delhi, New Delhi, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Delhi,New Delhi,India","institution_ids":["https://openalex.org/I68891433"]},{"raw_affiliation_string":"Indian Institute of Technology Delhi, New Delhi, India","institution_ids":["https://openalex.org/I68891433"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008011360","display_name":"Manan Suri","orcid":"https://orcid.org/0000-0003-1417-3570"},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Manan Suri","raw_affiliation_strings":["Indian Institute of Technology Delhi,New Delhi,India","Indian Institute of Technology Delhi, New Delhi, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Delhi,New Delhi,India","institution_ids":["https://openalex.org/I68891433"]},{"raw_affiliation_string":"Indian Institute of Technology Delhi, New Delhi, India","institution_ids":["https://openalex.org/I68891433"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.09475285,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"27","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7502989768981934},{"id":"https://openalex.org/keywords/systolic-array","display_name":"Systolic array","score":0.5873863697052002},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.4794272780418396},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4760596454143524},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.47265827655792236},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4540775716304779},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.41143298149108887},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41004183888435364},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.29471802711486816},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.1256970465183258}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7502989768981934},{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.5873863697052002},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.4794272780418396},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4760596454143524},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.47265827655792236},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4540775716304779},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.41143298149108887},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41004183888435364},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29471802711486816},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.1256970465183258},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/smacd58065.2023.10192216","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/smacd58065.2023.10192216","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2002885803","https://openalex.org/W2010202670","https://openalex.org/W2068469823","https://openalex.org/W2157587823","https://openalex.org/W2178102281","https://openalex.org/W2346824930","https://openalex.org/W2464177207","https://openalex.org/W2725159389","https://openalex.org/W2753463544","https://openalex.org/W2796625795","https://openalex.org/W2905515056","https://openalex.org/W2911491685","https://openalex.org/W4241841281","https://openalex.org/W4280635517","https://openalex.org/W6719768283","https://openalex.org/W6758823024"],"related_works":["https://openalex.org/W4240320454","https://openalex.org/W2611005572","https://openalex.org/W2154560316","https://openalex.org/W2105031241","https://openalex.org/W2001585562","https://openalex.org/W2963909880","https://openalex.org/W2077105843","https://openalex.org/W2112804590","https://openalex.org/W2140286994","https://openalex.org/W2904405156"],"abstract_inverted_index":{"In":[0,70],"recent":[1],"years,":[2],"hardware":[3],"accelerators":[4],"have":[5],"shown":[6],"significant":[7],"advantages":[8],"in":[9,19,33,67],"the":[10,28,62,79,82],"field":[11],"of":[12,30,40],"deep":[13],"neural":[14],"networks.":[15],"The":[16],"architecture":[17],"used":[18],"such":[20],"systems":[21],"has":[22],"high":[23],"memory":[24,31,41,54],"utilization.":[25],"To":[26],"make":[27],"most":[29],"technology":[32],"conjunction":[34],"with":[35,56],"compute":[36],"fabric,":[37],"careful":[38],"study":[39],"optimisation":[42],"is":[43,65],"thus":[44],"necessary.":[45],"NVSystolic,":[46],"a":[47,57],"heterogeneous":[48],"simulation":[49],"framework":[50,80],"based":[51],"on":[52],"reconfigurable":[53],"subsystems":[55],"systolic":[58,83],"array":[59],"serving":[60],"as":[61],"computing":[63],"unit,":[64],"presented":[66],"this":[68],"study.":[69],"particular,":[71],"Non-Volatile":[72],"Memory":[73],"(NVM)":[74],"can":[75],"be":[76],"modelled":[77],"by":[78],"for":[81],"array-based":[84],"accelerator.":[85]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}