{"id":"https://openalex.org/W2967183109","doi":"https://doi.org/10.1109/smacd.2019.8795299","title":"FPGA Based Modelling of an ADPLL Network","display_name":"FPGA Based Modelling of an ADPLL Network","publication_year":2019,"publication_date":"2019-07-01","ids":{"openalex":"https://openalex.org/W2967183109","doi":"https://doi.org/10.1109/smacd.2019.8795299","mag":"2967183109"},"language":"en","primary_location":{"id":"doi:10.1109/smacd.2019.8795299","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd.2019.8795299","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/10197/11204","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033143922","display_name":"C. Dooley","orcid":null},"institutions":[{"id":"https://openalex.org/I825935405","display_name":"Oceaneering International (United States)","ror":"https://ror.org/04hydf024","country_code":"US","type":"company","lineage":["https://openalex.org/I825935405"]},{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE","US"],"is_corresponding":true,"raw_author_name":"C. Dooley","raw_affiliation_strings":["School of Electrical &#x0026; Electronic Eneineering, University College, Dublin","School of Electrical & Electronic Eneineering, University College, Dublin"],"affiliations":[{"raw_affiliation_string":"School of Electrical &#x0026; Electronic Eneineering, University College, Dublin","institution_ids":["https://openalex.org/I825935405"]},{"raw_affiliation_string":"School of Electrical & Electronic Eneineering, University College, Dublin","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001003834","display_name":"Elena Blokhina","orcid":"https://orcid.org/0000-0002-4164-4350"},"institutions":[{"id":"https://openalex.org/I825935405","display_name":"Oceaneering International (United States)","ror":"https://ror.org/04hydf024","country_code":"US","type":"company","lineage":["https://openalex.org/I825935405"]},{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE","US"],"is_corresponding":false,"raw_author_name":"E. Blokhina","raw_affiliation_strings":["School of Electrical &#x0026; Electronic Eneineering, University College, Dublin","School of Electrical & Electronic Eneineering, University College, Dublin"],"affiliations":[{"raw_affiliation_string":"School of Electrical &#x0026; Electronic Eneineering, University College, Dublin","institution_ids":["https://openalex.org/I825935405"]},{"raw_affiliation_string":"School of Electrical & Electronic Eneineering, University College, Dublin","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056144613","display_name":"Brian Mulkeen","orcid":null},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]},{"id":"https://openalex.org/I825935405","display_name":"Oceaneering International (United States)","ror":"https://ror.org/04hydf024","country_code":"US","type":"company","lineage":["https://openalex.org/I825935405"]}],"countries":["IE","US"],"is_corresponding":false,"raw_author_name":"B. Mulkeen","raw_affiliation_strings":["School of Electrical &#x0026; Electronic Eneineering, University College, Dublin","School of Electrical & Electronic Eneineering, University College, Dublin"],"affiliations":[{"raw_affiliation_string":"School of Electrical &#x0026; Electronic Eneineering, University College, Dublin","institution_ids":["https://openalex.org/I825935405"]},{"raw_affiliation_string":"School of Electrical & Electronic Eneineering, University College, Dublin","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032777255","display_name":"Dimitri Galayko","orcid":"https://orcid.org/0000-0002-7056-7489"},"institutions":[{"id":"https://openalex.org/I51101395","display_name":"Universit\u00e9 Paris 1 Panth\u00e9on-Sorbonne","ror":"https://ror.org/002t25c44","country_code":"FR","type":"education","lineage":["https://openalex.org/I51101395"]},{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"D. Galayko","raw_affiliation_strings":["LIP6 Lab, Sorbonne Universit&#x00E9;","LIP6 Lab, Sorbonne Universit\u00e9"],"affiliations":[{"raw_affiliation_string":"LIP6 Lab, Sorbonne Universit&#x00E9;","institution_ids":["https://openalex.org/I39804081","https://openalex.org/I51101395"]},{"raw_affiliation_string":"LIP6 Lab, Sorbonne Universit\u00e9","institution_ids":["https://openalex.org/I39804081"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5033143922"],"corresponding_institution_ids":["https://openalex.org/I100930933","https://openalex.org/I825935405"],"apc_list":null,"apc_paid":null,"fwci":0.1206,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.46189293,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"289","last_page":"292"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9927999973297119,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9781000018119812,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8550314903259277},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7210007905960083},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.7023741602897644},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5632336735725403},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5468770861625671},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.14866101741790771}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8550314903259277},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7210007905960083},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.7023741602897644},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5632336735725403},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5468770861625671},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.14866101741790771}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/smacd.2019.8795299","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd.2019.8795299","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"},{"id":"pmh:oai:researchrepository.ucd.ie:10197/11204","is_oa":true,"landing_page_url":"http://hdl.handle.net/10197/11204","pdf_url":"http://hdl.handle.net/10197/11204","source":{"id":"https://openalex.org/S4306402280","display_name":"Research Repository UCD (University College Dublin)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I100930933","host_organization_name":"University College Dublin","host_organization_lineage":["https://openalex.org/I100930933"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference Publication"},{"id":"pmh:oai:HAL:hal-04031071v1","is_oa":false,"landing_page_url":"https://hal.science/hal-04031071","pdf_url":null,"source":{"id":"https://openalex.org/S4406922461","display_name":"SPIRE - Sciences Po Institutional REpository","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Jul 2019, Lausanne, Switzerland. pp.289-292, &#x27E8;10.1109/SMACD.2019.8795299&#x27E9;","raw_type":"Conference papers"}],"best_oa_location":{"id":"pmh:oai:researchrepository.ucd.ie:10197/11204","is_oa":true,"landing_page_url":"http://hdl.handle.net/10197/11204","pdf_url":"http://hdl.handle.net/10197/11204","source":{"id":"https://openalex.org/S4306402280","display_name":"Research Repository UCD (University College Dublin)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I100930933","host_organization_name":"University College Dublin","host_organization_lineage":["https://openalex.org/I100930933"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference Publication"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5799999833106995}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2967183109.pdf","grobid_xml":"https://content.openalex.org/works/W2967183109.grobid-xml"},"referenced_works_count":6,"referenced_works":["https://openalex.org/W2111991111","https://openalex.org/W2118232269","https://openalex.org/W2135663303","https://openalex.org/W2887823254","https://openalex.org/W3001576521","https://openalex.org/W4240491620"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"and":[3,26,44],"compares":[4],"the":[5,41],"implementation":[6],"of":[7,10,46],"a":[8,51],"number":[9],"FPGA":[11],"based":[12],"ADPLL":[13,24,48],"network":[14],"prototyping":[15],"architectures.":[16],"Networks":[17],"are":[18],"then":[19],"created":[20],"using":[21],"three":[22],"different":[23],"implementations":[25],"tests":[27],"performed":[28],"on":[29,32],"each.":[30],"Based":[31],"these":[33],"test":[34],"results,":[35],"comparison":[36],"is":[37],"made":[38],"to":[39],"both":[40],"expected":[42],"performance":[43],"role":[45],"each":[47],"design":[49],"as":[50],"development":[52],"tool.":[53]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}
