{"id":"https://openalex.org/W2968481429","doi":"https://doi.org/10.1109/smacd.2019.8795262","title":"A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects","display_name":"A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects","publication_year":2019,"publication_date":"2019-07-01","ids":{"openalex":"https://openalex.org/W2968481429","doi":"https://doi.org/10.1109/smacd.2019.8795262","mag":"2968481429"},"language":"en","primary_location":{"id":"doi:10.1109/smacd.2019.8795262","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd.2019.8795262","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041568803","display_name":"Dimitrios Garyfallou","orcid":"https://orcid.org/0000-0001-8616-2366"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Dimitrios Garyfallou","raw_affiliation_strings":["University of Thessaly, Volos, Greece","Department of Electrical and Computer Engineering, University of Thessaly, Volos, Greece"],"affiliations":[{"raw_affiliation_string":"University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041803182","display_name":"Charalampos Antoniadis","orcid":"https://orcid.org/0000-0002-5902-5240"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Charalampos Antoniadis","raw_affiliation_strings":["University of Thessaly, Volos, Greece","Department of Electrical and Computer Engineering, University of Thessaly, Volos, Greece"],"affiliations":[{"raw_affiliation_string":"University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008228117","display_name":"Nestor Evmorfopoulos","orcid":"https://orcid.org/0000-0002-6968-0222"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Nestor Evmorfopoulos","raw_affiliation_strings":["University of Thessaly, Volos, Greece","Department of Electrical and Computer Engineering, University of Thessaly, Volos, Greece"],"affiliations":[{"raw_affiliation_string":"University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065041833","display_name":"Georgios Stamoulis","orcid":"https://orcid.org/0000-0001-7248-8197"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Georgios Stamoulis","raw_affiliation_strings":["University of Thessaly, Volos, Greece","Department of Electrical and Computer Engineering, University of Thessaly, Volos, Greece"],"affiliations":[{"raw_affiliation_string":"University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5041568803"],"corresponding_institution_ids":["https://openalex.org/I145722265"],"apc_list":null,"apc_paid":null,"fwci":0.1206,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.46302784,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"89","last_page":"92"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8824862241744995},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7301074266433716},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5948896408081055},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4221542477607727},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4103759527206421},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.23816758394241333}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8824862241744995},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7301074266433716},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5948896408081055},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4221542477607727},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4103759527206421},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.23816758394241333}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/smacd.2019.8795262","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd.2019.8795262","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"},{"id":"pmh:oai:ir.lib.uth.gr:11615/71977","is_oa":false,"landing_page_url":"http://hdl.handle.net/11615/71977","pdf_url":null,"source":{"id":"https://openalex.org/S4306400243","display_name":"University of Thessaly Institutional Repository (University of Thessaly)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I145722265","host_organization_name":"University of Thessaly","host_organization_lineage":["https://openalex.org/I145722265"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings","raw_type":"conferenceItem"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1594588430","https://openalex.org/W1952921853","https://openalex.org/W1974368829","https://openalex.org/W1984588379","https://openalex.org/W2044330888","https://openalex.org/W2108665876","https://openalex.org/W2114505736","https://openalex.org/W2119098576","https://openalex.org/W2122901855","https://openalex.org/W2128919817","https://openalex.org/W2139030761","https://openalex.org/W2163288592","https://openalex.org/W2886183992","https://openalex.org/W2909720636","https://openalex.org/W4245942234","https://openalex.org/W6661758482","https://openalex.org/W6680641309"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W4283025278","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2082432309","https://openalex.org/W2134640991","https://openalex.org/W3027318491","https://openalex.org/W1979789826","https://openalex.org/W101478184","https://openalex.org/W1986774039"],"abstract_inverted_index":{"Signoff":[0],"timing":[1,27,67,126],"analysis":[2,28,127],"is":[3,48,62],"essential":[4],"in":[5,103,115],"order":[6],"to":[7,88,140],"verify":[8],"the":[9,23,43,125,135,150],"proper":[10],"operation":[11],"of":[12,29,42,57,78,128,149,158],"VLSI":[13],"circuits.":[14],"As":[15],"process":[16],"technologies":[17],"scale":[18],"down":[19],"towards":[20],"nanometer":[21],"regimes,":[22],"fast":[24],"and":[25,95],"accurate":[26],"interconnects":[30],"has":[31],"become":[32],"crucial,":[33],"since":[34],"interconnect":[35,60],"delay":[36],"represents":[37],"an":[38],"increasingly":[39],"dominant":[40],"portion":[41],"overall":[44],"circuit":[45],"delay.":[46],"It":[47],"a":[49,90,120,154],"common":[50],"view":[51],"that":[52,107,134],"traditional":[53],"SPICE":[54,146],"transient":[55,147],"simulation":[56,110,142,148],"very":[58],"large":[59],"models":[61],"not":[63],"feasible":[64],"for":[65,124],"full-chip":[66],"analysis,":[68],"while":[69],"static":[70],"Elmore-based":[71],"methods":[72],"can":[73],"be":[74],"inaccurate":[75],"by":[76],"orders":[77],"magnitude.":[79],"Model":[80],"Order":[81],"Reduction":[82],"(MOR)":[83],"techniques":[84,101],"are":[85],"typically":[86],"employed":[87],"provide":[89],"good":[91],"compromise":[92],"between":[93],"accuracy":[94,157],"performance.":[96],"However,":[97],"all":[98],"established":[99],"MOR":[100,122],"result":[102],"dense":[104],"system":[105],"matrices":[106],"render":[108],"their":[109],"impractical.":[111],"To":[112],"this":[113,116],"end,":[114],"paper":[117],"we":[118],"propose":[119],"sparsity-aware":[121],"methodology":[123],"complex":[129],"interconnects.":[130],"Experimental":[131],"results":[132],"demonstrate":[133],"proposed":[136],"method":[137],"achieves":[138],"up":[139],"30x":[141],"time":[143],"speedups":[144],"over":[145],"initial":[151],"model,":[152],"maintaining":[153],"reasonable":[155],"typical":[156],"4%.":[159]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}