{"id":"https://openalex.org/W2967850598","doi":"https://doi.org/10.1109/smacd.2019.8795227","title":"A Structure-Based Methodology for Analog Layout Generation","display_name":"A Structure-Based Methodology for Analog Layout Generation","publication_year":2019,"publication_date":"2019-07-01","ids":{"openalex":"https://openalex.org/W2967850598","doi":"https://doi.org/10.1109/smacd.2019.8795227","mag":"2967850598"},"language":"en","primary_location":{"id":"doi:10.1109/smacd.2019.8795227","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd.2019.8795227","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020872454","display_name":"Yu\u2010Hsien Chen","orcid":"https://orcid.org/0000-0002-9751-2250"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yu-Hsien Chen","raw_affiliation_strings":["National Central University, Jung-Li City, Taiwan, ROC","Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan, ROC"],"affiliations":[{"raw_affiliation_string":"National Central University, Jung-Li City, Taiwan, ROC","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, National Central University, Jung-Li City, Taiwan, ROC","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088127989","display_name":"Hao-Yu Chi","orcid":"https://orcid.org/0000-0002-7719-0119"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hao-Yu Chi","raw_affiliation_strings":["Inst. of Electronics, National Chiao Tung University, Hsin-Chu City, Taiwan, ROC"],"affiliations":[{"raw_affiliation_string":"Inst. of Electronics, National Chiao Tung University, Hsin-Chu City, Taiwan, ROC","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006431356","display_name":"Ling-Yen Song","orcid":"https://orcid.org/0000-0002-0146-9746"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ling-Yen Song","raw_affiliation_strings":["Inst. of Electronics, National Chiao Tung University, Hsin-Chu City, Taiwan, ROC"],"affiliations":[{"raw_affiliation_string":"Inst. of Electronics, National Chiao Tung University, Hsin-Chu City, Taiwan, ROC","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052798292","display_name":"Chien\u2010Nan Jimmy Liu","orcid":"https://orcid.org/0000-0002-4907-898X"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chien-Nan Jimmy Liu","raw_affiliation_strings":["Inst. of Electronics, National Chiao Tung University, Hsin-Chu City, Taiwan, ROC"],"affiliations":[{"raw_affiliation_string":"Inst. of Electronics, National Chiao Tung University, Hsin-Chu City, Taiwan, ROC","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021615416","display_name":"Hung-Ming Chen","orcid":"https://orcid.org/0000-0001-8173-3131"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Ming Chen","raw_affiliation_strings":["Inst. of Electronics, National Chiao Tung University, Hsin-Chu City, Taiwan, ROC"],"affiliations":[{"raw_affiliation_string":"Inst. of Electronics, National Chiao Tung University, Hsin-Chu City, Taiwan, ROC","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5020872454"],"corresponding_institution_ids":["https://openalex.org/I22265921"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.07219401,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"33","last_page":"36"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9440791010856628},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7605838179588318},{"id":"https://openalex.org/keywords/design-layout-record","display_name":"Design layout record","score":0.7519186735153198},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6476332545280457},{"id":"https://openalex.org/keywords/page-layout","display_name":"Page layout","score":0.6464390754699707},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.6075858473777771},{"id":"https://openalex.org/keywords/ic-layout-editor","display_name":"IC layout editor","score":0.6033508777618408},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.6017231345176697},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.5868047475814819},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5657109022140503},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.49817347526550293},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.4480493664741516},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.37374347448349},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34918373823165894},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.27662909030914307},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.24286913871765137},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23101294040679932},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.211465984582901},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.1861274242401123},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1449461281299591},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08120834827423096}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9440791010856628},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7605838179588318},{"id":"https://openalex.org/C179145894","wikidata":"https://www.wikidata.org/wiki/Q5264353","display_name":"Design layout record","level":5,"score":0.7519186735153198},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6476332545280457},{"id":"https://openalex.org/C188985296","wikidata":"https://www.wikidata.org/wiki/Q868954","display_name":"Page layout","level":2,"score":0.6464390754699707},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.6075858473777771},{"id":"https://openalex.org/C5546195","wikidata":"https://www.wikidata.org/wiki/Q5969842","display_name":"IC layout editor","level":5,"score":0.6033508777618408},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.6017231345176697},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.5868047475814819},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5657109022140503},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.49817347526550293},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.4480493664741516},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.37374347448349},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34918373823165894},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.27662909030914307},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.24286913871765137},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23101294040679932},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.211465984582901},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.1861274242401123},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1449461281299591},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08120834827423096},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C112698675","wikidata":"https://www.wikidata.org/wiki/Q37038","display_name":"Advertising","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/smacd.2019.8795227","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd.2019.8795227","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1976154696","https://openalex.org/W1980984060","https://openalex.org/W1983136098","https://openalex.org/W1993763736","https://openalex.org/W1996605065","https://openalex.org/W2034646262","https://openalex.org/W2065257040","https://openalex.org/W2067870394","https://openalex.org/W2076974297","https://openalex.org/W2097345923","https://openalex.org/W2099265142","https://openalex.org/W2111776955","https://openalex.org/W2116989584","https://openalex.org/W2147950839","https://openalex.org/W2292755228","https://openalex.org/W2381518922","https://openalex.org/W2624111906","https://openalex.org/W2792627863","https://openalex.org/W2895284909","https://openalex.org/W3141126213","https://openalex.org/W3142330788","https://openalex.org/W3174668475","https://openalex.org/W4249900664","https://openalex.org/W6669974401","https://openalex.org/W6739300425"],"related_works":["https://openalex.org/W2091329789","https://openalex.org/W1605062719","https://openalex.org/W2376028644","https://openalex.org/W2044122268","https://openalex.org/W2162651506","https://openalex.org/W1565715208","https://openalex.org/W1964352816","https://openalex.org/W2102933388","https://openalex.org/W2583707817","https://openalex.org/W1605542055"],"abstract_inverted_index":{"In":[0,71],"order":[1],"to":[2,40,52,103,152],"speed":[3],"up":[4],"analog":[5,8,80,130],"design":[6,26,44,55,66,113],"cycles,":[7],"layout":[9,47,81,118,156],"automation":[10],"is":[11,49,150],"a":[12,36,76,87],"popular":[13],"research":[14],"in":[15,143],"recent":[16],"years.":[17],"However,":[18],"most":[19],"previous":[20],"works":[21],"assume":[22],"that":[23,90],"the":[24,42,54,92,105,116,121,126,144,147,154,164],"required":[25,43,62,155],"constraints":[27,114],"are":[28,61,132],"given":[29],"by":[30],"users":[31],"manually.":[32],"Designers":[33],"still":[34,162],"take":[35],"lot":[37],"of":[38,128],"time":[39],"fill-in":[41],"information.":[45],"Template-based":[46],"generation":[48],"another":[50],"approach":[51],"consider":[53],"constraints,":[56],"but":[57],"considerable":[58],"development":[59],"efforts":[60],"for":[63,79,115],"each":[64,68],"new":[65,69],"and":[67,110,135,161],"technology.":[70],"this":[72],"paper,":[73],"we":[74],"propose":[75],"structure-based":[77],"methodology":[78,84],"generation.":[82],"This":[83],"starts":[85],"from":[86,123],"structure":[88,124],"analysis":[89],"divides":[91],"circuit":[93],"netlist":[94],"into":[95],"several":[96],"building":[97],"blocks":[98],"automatically.":[99],"It":[100],"can":[101],"help":[102,122],"reduce":[104],"dependence":[106],"on":[107],"users'":[108,159],"input":[109],"generate":[111,153],"corresponding":[112],"succeeding":[117],"steps.":[119],"With":[120],"analysis,":[125],"layouts":[127],"those":[129],"structures":[131],"generated,":[133],"placed,":[134],"routed":[136],"automatically":[137],"with":[138],"proper":[139],"constraints.":[140],"As":[141],"shown":[142],"demo":[145],"cases,":[146],"proposed":[148],"flow":[149],"able":[151],"accurately":[157],"without":[158],"intervention":[160],"keeps":[163],"post-layout":[165],"performance":[166],"within":[167],"specifications.":[168]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
