{"id":"https://openalex.org/W2886559659","doi":"https://doi.org/10.1109/smacd.2018.8434901","title":"Statistical Simulations of Delay Propagation in Large Scale Circuits Using Graph Traversal and Kernel Function Decomposition","display_name":"Statistical Simulations of Delay Propagation in Large Scale Circuits Using Graph Traversal and Kernel Function Decomposition","publication_year":2018,"publication_date":"2018-07-01","ids":{"openalex":"https://openalex.org/W2886559659","doi":"https://doi.org/10.1109/smacd.2018.8434901","mag":"2886559659"},"language":"en","primary_location":{"id":"doi:10.1109/smacd.2018.8434901","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd.2018.8434901","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/10197/9827","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062982927","display_name":"Jennifer Freeley","orcid":null},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Jennifer Freeley","raw_affiliation_strings":["University College Dublin, School of Electrical and Electronic Engineering, Ireland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University College Dublin, School of Electrical and Electronic Engineering, Ireland","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073311353","display_name":"Dmvtro Mishagli","orcid":null},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Dmvtro Mishagli","raw_affiliation_strings":["University College Dublin, School of Electrical and Electronic Engineering, Ireland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University College Dublin, School of Electrical and Electronic Engineering, Ireland","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090084602","display_name":"Tom Brazil","orcid":null},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Tom Brazil","raw_affiliation_strings":["University College Dublin, School of Electrical and Electronic Engineering, Ireland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University College Dublin, School of Electrical and Electronic Engineering, Ireland","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001003834","display_name":"Elena Blokhina","orcid":"https://orcid.org/0000-0002-4164-4350"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Elena Blokhina","raw_affiliation_strings":["University College Dublin, School of Electrical and Electronic Engineering, Ireland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University College Dublin, School of Electrical and Electronic Engineering, Ireland","institution_ids":["https://openalex.org/I100930933"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.5238,"has_fulltext":true,"cited_by_count":6,"citation_normalized_percentile":{"value":0.67909217,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"213","last_page":"216"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5761945247650146},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5566186904907227},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.5389251708984375},{"id":"https://openalex.org/keywords/tree-traversal","display_name":"Tree traversal","score":0.5363197922706604},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5202711224555969},{"id":"https://openalex.org/keywords/functional-decomposition","display_name":"Functional decomposition","score":0.5121030807495117},{"id":"https://openalex.org/keywords/gaussian","display_name":"Gaussian","score":0.4583738148212433},{"id":"https://openalex.org/keywords/probability-density-function","display_name":"Probability density function","score":0.42753443121910095},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4180552661418915},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.35668230056762695},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.35350099205970764},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.1245880126953125}],"concepts":[{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5761945247650146},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5566186904907227},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.5389251708984375},{"id":"https://openalex.org/C140745168","wikidata":"https://www.wikidata.org/wiki/Q1210082","display_name":"Tree traversal","level":2,"score":0.5363197922706604},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5202711224555969},{"id":"https://openalex.org/C12145135","wikidata":"https://www.wikidata.org/wiki/Q5215396","display_name":"Functional decomposition","level":2,"score":0.5121030807495117},{"id":"https://openalex.org/C163716315","wikidata":"https://www.wikidata.org/wiki/Q901177","display_name":"Gaussian","level":2,"score":0.4583738148212433},{"id":"https://openalex.org/C197055811","wikidata":"https://www.wikidata.org/wiki/Q207522","display_name":"Probability density function","level":2,"score":0.42753443121910095},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4180552661418915},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.35668230056762695},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.35350099205970764},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.1245880126953125},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/smacd.2018.8434901","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd.2018.8434901","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"},{"id":"pmh:oai:researchrepository.ucd.ie:10197/9827","is_oa":true,"landing_page_url":"http://hdl.handle.net/10197/9827","pdf_url":"http://hdl.handle.net/10197/9827","source":{"id":"https://openalex.org/S4306402280","display_name":"Research Repository UCD (University College Dublin)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I100930933","host_organization_name":"University College Dublin","host_organization_lineage":["https://openalex.org/I100930933"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference Publication"}],"best_oa_location":{"id":"pmh:oai:researchrepository.ucd.ie:10197/9827","is_oa":true,"landing_page_url":"http://hdl.handle.net/10197/9827","pdf_url":"http://hdl.handle.net/10197/9827","source":{"id":"https://openalex.org/S4306402280","display_name":"Research Repository UCD (University College Dublin)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I100930933","host_organization_name":"University College Dublin","host_organization_lineage":["https://openalex.org/I100930933"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference Publication"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G6586979110","display_name":null,"funder_award_id":"13/RC/2077","funder_id":"https://openalex.org/F4320335322","funder_display_name":"European Regional Development Fund"},{"id":"https://openalex.org/G7226090481","display_name":null,"funder_award_id":"13/RC/2077","funder_id":"https://openalex.org/F4320320847","funder_display_name":"Science Foundation Ireland"}],"funders":[{"id":"https://openalex.org/F4320320847","display_name":"Science Foundation Ireland","ror":"https://ror.org/0271asj38"},{"id":"https://openalex.org/F4320335322","display_name":"European Regional Development Fund","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2886559659.pdf","grobid_xml":"https://content.openalex.org/works/W2886559659.grobid-xml"},"referenced_works_count":16,"referenced_works":["https://openalex.org/W658677875","https://openalex.org/W1483017465","https://openalex.org/W1667165204","https://openalex.org/W1966741973","https://openalex.org/W1967709031","https://openalex.org/W2000688936","https://openalex.org/W2018697056","https://openalex.org/W2073368686","https://openalex.org/W2158750015","https://openalex.org/W2163262735","https://openalex.org/W2246821188","https://openalex.org/W2284954312","https://openalex.org/W2403550060","https://openalex.org/W2482869441","https://openalex.org/W2735300240","https://openalex.org/W4244015912"],"related_works":["https://openalex.org/W29481652","https://openalex.org/W4248668797","https://openalex.org/W2110968362","https://openalex.org/W4238178324","https://openalex.org/W3141297747","https://openalex.org/W2106889348","https://openalex.org/W2111485030","https://openalex.org/W4390345338","https://openalex.org/W96064250","https://openalex.org/W1797398192"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"propose":[4],"a":[5,40,53,76,92,96,116],"new":[6,26,41],"methodology":[7],"to":[8,47,67,114],"determine":[9],"the":[10,17,29,32,59,71,83,89,105,121],"delay":[11,49,85,124],"of":[12,19,31,43,58,65,82,91,99,123],"combinational":[13,127],"logic":[14],"circuits":[15],"within":[16],"framework":[18],"statistical":[20],"static":[21],"timing":[22,33],"analysis":[23],"(SSTA).":[24],"A":[25],"algorithm":[27,119],"for":[28,75,120],"traversing":[30],"graph":[34],"is":[35,86,102,109],"created":[36],"and":[37,62,104,131],"combined":[38],"with":[39],"technique":[42],"kernel":[44,100],"function":[45],"decomposition":[46],"find":[48],"propagation":[50,125],"through":[51],"such":[52],"circuit.":[54],"Assuming":[55],"initial":[56,106],"delays":[57],"input":[60],"signals":[61],"operation":[63],"time":[64],"gates":[66],"be":[68],"normally":[69],"distributed,":[70],"exact":[72],"analytical":[73],"solution":[74],"non-Gaussian":[77,93],"probability":[78],"density":[79],"functions":[80,101],"(PDF)":[81],"resulting":[84],"obtained.":[87],"Then,":[88],"approximation":[90],"PDF":[94],"by":[95],"linear":[97],"combination":[98],"proposed,":[103],"Gaussian":[107],"assumption":[108],"relaxed.":[110],"This":[111],"allowed":[112],"us":[113],"build":[115],"novel":[117],"closed-loop":[118],"calculation":[122],"in":[126],"circuits.":[128],"Possible":[129],"extensions":[130],"future":[132],"steps":[133],"are":[134],"discussed.":[135]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
