{"id":"https://openalex.org/W2887829944","doi":"https://doi.org/10.1109/smacd.2018.8434883","title":"On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog Layouts","display_name":"On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog Layouts","publication_year":2018,"publication_date":"2018-07-01","ids":{"openalex":"https://openalex.org/W2887829944","doi":"https://doi.org/10.1109/smacd.2018.8434883","mag":"2887829944"},"language":"en","primary_location":{"id":"doi:10.1109/smacd.2018.8434883","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd.2018.8434883","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062117190","display_name":"Po-Cheng Pan","orcid":"https://orcid.org/0000-0002-8626-1249"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Po-Cheng Pan","raw_affiliation_strings":["Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103396230","display_name":"Hung\u2010Wen Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Wen Huang","raw_affiliation_strings":["Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067537031","display_name":"Chien-Chia Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chien-Chia Huang","raw_affiliation_strings":["Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061799084","display_name":"Abhishek Patyal","orcid":"https://orcid.org/0000-0001-7094-7601"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Abhishek Patyal","raw_affiliation_strings":["Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021615416","display_name":"Hung-Ming Chen","orcid":"https://orcid.org/0000-0001-8173-3131"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Ming Chen","raw_affiliation_strings":["Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073936068","display_name":"Tsun-Yu Yang","orcid":"https://orcid.org/0009-0002-8992-480X"},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tsun-Yu Yang","raw_affiliation_strings":["Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"181","last_page":"184"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9076501131057739},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.751153826713562},{"id":"https://openalex.org/keywords/partition","display_name":"Partition (number theory)","score":0.6059650182723999},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.5793250799179077},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5299808979034424},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.47573280334472656},{"id":"https://openalex.org/keywords/ic-layout-editor","display_name":"IC layout editor","score":0.4668216109275818},{"id":"https://openalex.org/keywords/template","display_name":"Template","score":0.4569336771965027},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.442902147769928},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3177148103713989},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.17771244049072266},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10746040940284729},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09880968928337097},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.08957678079605103}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9076501131057739},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.751153826713562},{"id":"https://openalex.org/C42812","wikidata":"https://www.wikidata.org/wiki/Q1082910","display_name":"Partition (number theory)","level":2,"score":0.6059650182723999},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.5793250799179077},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5299808979034424},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.47573280334472656},{"id":"https://openalex.org/C5546195","wikidata":"https://www.wikidata.org/wiki/Q5969842","display_name":"IC layout editor","level":5,"score":0.4668216109275818},{"id":"https://openalex.org/C82714645","wikidata":"https://www.wikidata.org/wiki/Q438331","display_name":"Template","level":2,"score":0.4569336771965027},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.442902147769928},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3177148103713989},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.17771244049072266},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10746040940284729},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09880968928337097},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.08957678079605103},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/smacd.2018.8434883","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd.2018.8434883","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16","score":0.7599999904632568}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1980793905","https://openalex.org/W1985820940","https://openalex.org/W1996605065","https://openalex.org/W2045221862","https://openalex.org/W2113341980","https://openalex.org/W2131602584","https://openalex.org/W2295569708","https://openalex.org/W2343593014","https://openalex.org/W2534998135","https://openalex.org/W2604893700","https://openalex.org/W3140592728"],"related_works":["https://openalex.org/W4292182797","https://openalex.org/W2091329789","https://openalex.org/W3080940989","https://openalex.org/W4287685600","https://openalex.org/W2583707817","https://openalex.org/W2045697850","https://openalex.org/W2148021977","https://openalex.org/W2304374807","https://openalex.org/W2904595763","https://openalex.org/W2253173388"],"abstract_inverted_index":{"In":[0,42,78],"order":[1],"to":[2,16,32,48,82,90,94,120],"generate":[3],"analog":[4,113],"layout":[5,35,50,75,85,102,114],"in":[6,71,98],"advanced":[7],"technology,":[8],"it":[9],"still":[10],"remains":[11],"lots":[12],"of":[13,20,57,65],"challenges":[14],"due":[15],"the":[17,45,54,66,72,99],"imprecise":[18],"estimation":[19,56],"critical":[21],"performance":[22,40,55],"parameters.":[23],"We":[24],"propose":[25],"an":[26],"upgraded":[27],"decision":[28],"making":[29],"framework,":[30],"PEDefer,":[31],"decompose":[33],"existing":[34,61],"into":[36],"decisive":[37],"components":[38],"for":[39],"estimation.":[41],"this":[43,109],"work,":[44],"objective":[46],"is":[47],"synthesize":[49],"solutions":[51],"based":[52],"on":[53],"user-defined":[58],"constraints":[59,64],"and":[60,74],"templates.":[62],"The":[63,105],"circuit":[67],"are":[68,118],"priorly":[69],"tackled":[70],"partition":[73],"enumeration":[76,103],"stage.":[77],"addition,":[79],"we":[80],"attempt":[81],"have":[83],"partial":[84],"pieces":[86],"as":[87],"exchangeable":[88],"blocks":[89],"perform":[91],"pseudo-post-simulation,":[92],"thus":[93],"put":[95],"simulation":[96,122],"factors":[97],"evaluation":[100],"during":[101],"strategy.":[104],"experiments":[106],"show":[107],"that":[108],"flow":[110],"guarantees":[111],"valid":[112],"results":[115],"whose":[116],"performances":[117],"closer":[119],"netlist-Ievel":[121],"than":[123],"manual":[124],"designed":[125],"or":[126],"migrated":[127],"layouts":[128],"with":[129],"minimal":[130],"overhead.":[131]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}