{"id":"https://openalex.org/W2479619403","doi":"https://doi.org/10.1109/smacd.2016.7520734","title":"Statistically-aided electronic design environment","display_name":"Statistically-aided electronic design environment","publication_year":2016,"publication_date":"2016-06-01","ids":{"openalex":"https://openalex.org/W2479619403","doi":"https://doi.org/10.1109/smacd.2016.7520734","mag":"2479619403"},"language":"en","primary_location":{"id":"doi:10.1109/smacd.2016.7520734","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd.2016.7520734","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052013569","display_name":"Carlos Gil Soriano","orcid":null},"institutions":[{"id":"https://openalex.org/I88060688","display_name":"Universidad Polit\u00e9cnica de Madrid","ror":"https://ror.org/03n6nwv02","country_code":"ES","type":"education","lineage":["https://openalex.org/I88060688"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Carlos Gil Soriano","raw_affiliation_strings":["Dpto. de Ingenier\u00eda Electr\u00f3nica, Technical University of Madrid, Spain"],"affiliations":[{"raw_affiliation_string":"Dpto. de Ingenier\u00eda Electr\u00f3nica, Technical University of Madrid, Spain","institution_ids":["https://openalex.org/I88060688"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068231777","display_name":"Pablo Ituero","orcid":"https://orcid.org/0000-0001-6448-7936"},"institutions":[{"id":"https://openalex.org/I88060688","display_name":"Universidad Polit\u00e9cnica de Madrid","ror":"https://ror.org/03n6nwv02","country_code":"ES","type":"education","lineage":["https://openalex.org/I88060688"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pablo Ituero","raw_affiliation_strings":["Dpto. de Ingenier\u00eda Electr\u00f3nica, Technical University of Madrid, Spain"],"affiliations":[{"raw_affiliation_string":"Dpto. de Ingenier\u00eda Electr\u00f3nica, Technical University of Madrid, Spain","institution_ids":["https://openalex.org/I88060688"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5052013569"],"corresponding_institution_ids":["https://openalex.org/I88060688"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05618418,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"13","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.755299985408783},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6373797655105591},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5682262778282166},{"id":"https://openalex.org/keywords/metric","display_name":"Metric (unit)","score":0.562152087688446},{"id":"https://openalex.org/keywords/grasp","display_name":"GRASP","score":0.5561001300811768},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5340766906738281},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5233182907104492},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.5174218416213989},{"id":"https://openalex.org/keywords/workflow","display_name":"Workflow","score":0.5012562274932861},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4815919101238251},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.451961874961853},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4372069835662842},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40731820464134216},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.276073157787323},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23285722732543945},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.20048534870147705},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1478906273841858},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.1397131085395813},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.08123898506164551}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.755299985408783},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6373797655105591},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5682262778282166},{"id":"https://openalex.org/C176217482","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Metric (unit)","level":2,"score":0.562152087688446},{"id":"https://openalex.org/C171268870","wikidata":"https://www.wikidata.org/wiki/Q1486676","display_name":"GRASP","level":2,"score":0.5561001300811768},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5340766906738281},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5233182907104492},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.5174218416213989},{"id":"https://openalex.org/C177212765","wikidata":"https://www.wikidata.org/wiki/Q627335","display_name":"Workflow","level":2,"score":0.5012562274932861},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4815919101238251},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.451961874961853},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4372069835662842},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40731820464134216},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.276073157787323},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23285722732543945},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.20048534870147705},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1478906273841858},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.1397131085395813},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.08123898506164551},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/smacd.2016.7520734","is_oa":false,"landing_page_url":"https://doi.org/10.1109/smacd.2016.7520734","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.44999998807907104,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W94194614","https://openalex.org/W621293842","https://openalex.org/W1638081485","https://openalex.org/W2120116751","https://openalex.org/W2125169487","https://openalex.org/W2127658298","https://openalex.org/W2132844001","https://openalex.org/W2134141201","https://openalex.org/W2187582022","https://openalex.org/W2503057153","https://openalex.org/W4254506919","https://openalex.org/W6603863532","https://openalex.org/W6678992168","https://openalex.org/W6687355067"],"related_works":["https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W2743305891","https://openalex.org/W2126983197","https://openalex.org/W2070693700","https://openalex.org/W2078506771","https://openalex.org/W2134664711","https://openalex.org/W2098316714","https://openalex.org/W2102933388","https://openalex.org/W1965232212"],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"SAEDE":[3],"(Statistically-Aided":[4],"Electronic":[5],"Design":[6],"Environment),":[7],"a":[8,34,46],"framework":[9],"targeted":[10],"to":[11,71,91,95],"perform":[12],"advanced":[13],"statistical":[14,68],"analysis":[15],"within":[16],"an":[17],"ASIC":[18,72],"design":[19,32,73],"workflow,":[20],"linking":[21],"together":[22],"circuit":[23,47,92],"performance":[24,48,93],"with":[25],"technological":[26],"parameters.":[27,62],"A":[28],"driving":[29],"example,":[30],"the":[31,50,53],"of":[33,52],"10-stage":[35],"delay":[36],"line,":[37],"is":[38],"conducted.":[39],"The":[40],"study":[41],"goals":[42],"are":[43,86],"two-fold:":[44],"extract":[45],"metric,":[49],"spread":[51],"stage-delay,":[54],"and":[55,80],"determine":[56],"its":[57],"most":[58],"sensitive":[59],"BSIM4":[60,89],"transistor":[61],"To":[63],"achieve":[64],"these":[65],"goals,":[66],"two":[67],"tools,":[69],"new":[70],"work-flow,":[74],"have":[75],"been":[76],"used:":[77],"Skew-Normal":[78],"inference":[79],"BAHSIC":[81],"feature":[82],"selection.":[83],"Consistent":[84],"results":[85],"obtained,":[87],"relating":[88],"parameters":[90],"impossible":[94],"grasp":[96],"by":[97],"analytical":[98],"terms.":[99]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
