{"id":"https://openalex.org/W2964929543","doi":"https://doi.org/10.1109/slip.2019.8771330","title":"An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems","display_name":"An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems","publication_year":2019,"publication_date":"2019-06-01","ids":{"openalex":"https://openalex.org/W2964929543","doi":"https://doi.org/10.1109/slip.2019.8771330","mag":"2964929543"},"language":"en","primary_location":{"id":"doi:10.1109/slip.2019.8771330","is_oa":false,"landing_page_url":"https://doi.org/10.1109/slip.2019.8771330","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080499552","display_name":"Chak-Wa Pui","orcid":null},"institutions":[{"id":"https://openalex.org/I889458895","display_name":"University of Hong Kong","ror":"https://ror.org/02zhqgq86","country_code":"HK","type":"education","lineage":["https://openalex.org/I889458895"]}],"countries":["HK"],"is_corresponding":true,"raw_author_name":"Chak-Wa Pui","raw_affiliation_strings":["CUHK"],"affiliations":[{"raw_affiliation_string":"CUHK","institution_ids":["https://openalex.org/I889458895"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100717611","display_name":"Gang Wu","orcid":"https://orcid.org/0000-0001-9595-527X"},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Gang Wu","raw_affiliation_strings":["Synopsys Inc"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc","institution_ids":["https://openalex.org/I1335490905"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049383677","display_name":"Freddy Y. C. Mang","orcid":null},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Freddy Y. C. Mang","raw_affiliation_strings":["Synopsys Inc"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc","institution_ids":["https://openalex.org/I1335490905"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070795253","display_name":"Evangeline F. Y. Young","orcid":"https://orcid.org/0000-0003-0623-1590"},"institutions":[{"id":"https://openalex.org/I889458895","display_name":"University of Hong Kong","ror":"https://ror.org/02zhqgq86","country_code":"HK","type":"education","lineage":["https://openalex.org/I889458895"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Evangeline F. Y. Young","raw_affiliation_strings":["CUHK"],"affiliations":[{"raw_affiliation_string":"CUHK","institution_ids":["https://openalex.org/I889458895"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5080499552"],"corresponding_institution_ids":["https://openalex.org/I889458895"],"apc_list":null,"apc_paid":null,"fwci":0.8346,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.73968125,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8667901754379272},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7059746980667114},{"id":"https://openalex.org/keywords/time-division-multiplexing","display_name":"Time-division multiplexing","score":0.6045536994934082},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.5790770649909973},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5775789022445679},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.5330687165260315},{"id":"https://openalex.org/keywords/linear-programming","display_name":"Linear programming","score":0.48756760358810425},{"id":"https://openalex.org/keywords/discretization","display_name":"Discretization","score":0.46845006942749023},{"id":"https://openalex.org/keywords/system-time","display_name":"System time","score":0.45386409759521484},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3293907046318054},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3239815831184387},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.23870059847831726},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12775638699531555},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0670437216758728}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8667901754379272},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7059746980667114},{"id":"https://openalex.org/C50661577","wikidata":"https://www.wikidata.org/wiki/Q901831","display_name":"Time-division multiplexing","level":3,"score":0.6045536994934082},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.5790770649909973},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5775789022445679},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.5330687165260315},{"id":"https://openalex.org/C41045048","wikidata":"https://www.wikidata.org/wiki/Q202843","display_name":"Linear programming","level":2,"score":0.48756760358810425},{"id":"https://openalex.org/C73000952","wikidata":"https://www.wikidata.org/wiki/Q17007827","display_name":"Discretization","level":2,"score":0.46845006942749023},{"id":"https://openalex.org/C192082776","wikidata":"https://www.wikidata.org/wiki/Q7663751","display_name":"System time","level":3,"score":0.45386409759521484},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3293907046318054},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3239815831184387},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.23870059847831726},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12775638699531555},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0670437216758728},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C60229501","wikidata":"https://www.wikidata.org/wiki/Q18822","display_name":"Global Positioning System","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/slip.2019.8771330","is_oa":false,"landing_page_url":"https://doi.org/10.1109/slip.2019.8771330","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1992578807","https://openalex.org/W2068041061","https://openalex.org/W2075490772","https://openalex.org/W2098841537","https://openalex.org/W2148658001","https://openalex.org/W2261042505","https://openalex.org/W2584883722","https://openalex.org/W2585649541","https://openalex.org/W2789489838","https://openalex.org/W2793619867","https://openalex.org/W2899799513","https://openalex.org/W6756572453"],"related_works":["https://openalex.org/W2258948885","https://openalex.org/W2171071906","https://openalex.org/W4226230195","https://openalex.org/W1996671501","https://openalex.org/W2054922540","https://openalex.org/W2798557478","https://openalex.org/W2100133898","https://openalex.org/W3173929316","https://openalex.org/W3109783261","https://openalex.org/W2613031556"],"abstract_inverted_index":{"To":[0],"increase":[1],"the":[2,30,34,50,111,125,142],"utilization":[3],"of":[4,23,45,52,151],"FPGAs":[5],"in":[6,68],"multi-FPGA":[7,69],"based":[8,70],"systems,":[9],"time-division":[10],"multiplexing":[11],"(TDM)":[12],"is":[13,170],"a":[14,20,53,74,92,99,103,115,152],"widely":[15],"used":[16],"technique":[17],"to":[18,63,77,82,173],"accommodate":[19],"large":[21],"number":[22],"inter-FPGA":[24,35,155],"signals.":[25],"However,":[26],"with":[27,177],"this":[28,56],"technique,":[29],"delay":[31],"imposed":[32],"by":[33,114,146],"connections":[36],"becomes":[37],"significant.":[38],"Previous":[39],"research":[40],"shows":[41],"that":[42,137],"TDM":[43],"ratio":[44],"signals":[46],"can":[47,140],"greatly":[48],"affect":[49],"performance":[51],"system.":[54],"In":[55,80],"paper,":[57],"we":[58,90,122],"extend":[59],"previous":[60],"problem":[61,126],"formulation":[62],"meet":[64],"more":[65],"general":[66],"constraints":[67],"systems":[71],"and":[72,88,108],"propose":[73,91],"novel":[75],"approach":[76,139,160],"solve":[78,124],"it.":[79],"particular,":[81],"optimize":[83],"system":[84,143],"clock":[85,144],"period":[86,145],"effectively":[87],"efficiently,":[89],"two-step":[93],"analytical":[94],"framework,":[95],"which":[96],"first":[97],"gives":[98],"continuous":[100],"result":[101,112],"using":[102,127],"non-linear":[104],"conjugate":[105],"gradient-based":[106],"method":[107,169],"then":[109],"finalizes":[110],"optimally":[113],"dynamic":[116],"programming-based":[117],"discretization":[118],"algorithm.":[119],"For":[120],"comparison,":[121],"also":[123],"an":[128],"integer":[129],"linear":[130],"programming":[131],"(ILP)-based":[132],"method.":[133],"Experimental":[134],"results":[135],"show":[136],"our":[138,159],"improve":[141],"about":[147],"7%":[148],"on":[149],"top":[150],"well":[153],"optimized":[154],"routing":[156],"result.":[157],"Moreover,":[158],"scales":[161],"for":[162,175],"designs":[163,176],"over":[164],"400K":[165],"nodes":[166],"while":[167],"ILP-based":[168],"not":[171],"able":[172],"finish":[174],"2K":[178],"nodes.":[179]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}