{"id":"https://openalex.org/W3151435834","doi":"https://doi.org/10.1109/slip.2011.6135433","title":"System interconnect design exploration for embedded MPSoCs","display_name":"System interconnect design exploration for embedded MPSoCs","publication_year":2011,"publication_date":"2011-06-01","ids":{"openalex":"https://openalex.org/W3151435834","doi":"https://doi.org/10.1109/slip.2011.6135433","mag":"3151435834"},"language":"en","primary_location":{"id":"doi:10.1109/slip.2011.6135433","is_oa":false,"landing_page_url":"https://doi.org/10.1109/slip.2011.6135433","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Workshop on System Level Interconnect Prediction","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113670446","display_name":"Chen-Ling Chou","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Chen-Ling Chou","raw_affiliation_strings":["Electrical and Computer Engineering, Carnegie Mellon University, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Carnegie Mellon University, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036227385","display_name":"Radu M\u0103rculescu","orcid":"https://orcid.org/0000-0003-1826-7646"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Radu Marculescu","raw_affiliation_strings":["Electrical and Computer Engineering, Carnegie Mellon University, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Carnegie Mellon University, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084255924","display_name":"\u00dcmit Y. Ogras","orcid":"https://orcid.org/0000-0002-5045-5535"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Umit Ogras","raw_affiliation_strings":["Intel Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102897547","display_name":"Satrajit Chatterjee","orcid":"https://orcid.org/0000-0001-8135-8378"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Satrajit Chatterjee","raw_affiliation_strings":["Intel Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007256099","display_name":"Michael Kishinevsky","orcid":"https://orcid.org/0000-0002-5593-9694"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Kishinevsky","raw_affiliation_strings":["Intel Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087140754","display_name":"Dmitrii Loukianov","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dmitrii Loukianov","raw_affiliation_strings":["Intel Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5113670446"],"corresponding_institution_ids":["https://openalex.org/I74973139"],"apc_list":null,"apc_paid":null,"fwci":0.3501,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.69283987,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"12","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.8829646706581116},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.7978025674819946},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7168408036231995},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.712202250957489},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.6639513373374939},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.5979275107383728},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5744733214378357},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.501276969909668},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.4721921682357788},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.47163721919059753},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4528655409812927},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.4114193618297577},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17877408862113953}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.8829646706581116},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.7978025674819946},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7168408036231995},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.712202250957489},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.6639513373374939},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.5979275107383728},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5744733214378357},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.501276969909668},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.4721921682357788},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.47163721919059753},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4528655409812927},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.4114193618297577},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17877408862113953},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/slip.2011.6135433","is_oa":false,"landing_page_url":"https://doi.org/10.1109/slip.2011.6135433","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Workshop on System Level Interconnect Prediction","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5400000214576721,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2114772983","https://openalex.org/W2123184444","https://openalex.org/W2127430446","https://openalex.org/W2132249049","https://openalex.org/W2148866534","https://openalex.org/W2159800085","https://openalex.org/W2160642395","https://openalex.org/W3144369919","https://openalex.org/W4230447822","https://openalex.org/W4246337488","https://openalex.org/W4247314338","https://openalex.org/W4256229502","https://openalex.org/W4292019270","https://openalex.org/W6603067666","https://openalex.org/W6675673416","https://openalex.org/W6679432905"],"related_works":["https://openalex.org/W1934552808","https://openalex.org/W2293483919","https://openalex.org/W2587830891","https://openalex.org/W4234221021","https://openalex.org/W2548514518","https://openalex.org/W2092181573","https://openalex.org/W2119904701","https://openalex.org/W4230458348","https://openalex.org/W3198758847","https://openalex.org/W2576551918"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,17],"new":[4],"approach":[5,58],"for":[6,25,59],"system":[7],"interconnect":[8],"design":[9,28,42],"exploration":[10,30],"of":[11,75],"application-specific":[12],"multi-processor":[13],"systems-on-chip":[14],"(MPSoCs).":[15],"As":[16],"novel":[18],"contribution,":[19],"we":[20,53],"develop":[21],"an":[22,56,89],"analytical":[23,77],"model":[24,78],"network-based":[26],"communication":[27],"space":[29],"and":[31,48,88],"generate":[32],"fabric":[33],"solutions":[34,62],"with":[35,63],"optimal":[36],"cost-performance":[37],"trade-offs,":[38],"while":[39],"considering":[40],"various":[41],"constrains,":[43],"such":[44],"as":[45],"power,":[46],"area,":[47],"wirelength.":[49],"For":[50],"large":[51],"systems,":[52],"also":[54],"propose":[55],"efficient":[57],"obtaining":[60],"competitive":[61],"significant":[64],"less":[65],"computation":[66],"time":[67],"compared":[68],"to":[69],"the":[70],"exhaustive":[71],"approach.":[72],"The":[73],"accuracy":[74],"our":[76],"is":[79],"validated":[80],"via":[81],"SystemC":[82],"simulation":[83],"using":[84],"several":[85],"synthetic":[86],"applications":[87],"industrial":[90],"SoC":[91],"design.":[92]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
