{"id":"https://openalex.org/W3118304226","doi":"https://doi.org/10.1109/siu49456.2020.9302072","title":"A Hardware Accelerated Packet Classifier Design for A Network Router","display_name":"A Hardware Accelerated Packet Classifier Design for A Network Router","publication_year":2020,"publication_date":"2020-10-05","ids":{"openalex":"https://openalex.org/W3118304226","doi":"https://doi.org/10.1109/siu49456.2020.9302072","mag":"3118304226"},"language":"en","primary_location":{"id":"doi:10.1109/siu49456.2020.9302072","is_oa":false,"landing_page_url":"https://doi.org/10.1109/siu49456.2020.9302072","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 28th Signal Processing and Communications Applications Conference (SIU)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5098107402","display_name":"O\u011fuzhan \u00c7\u0131k","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"O\u011fuzhan \u00c7\u0131k","raw_affiliation_strings":["Donan&#x0131;m Geli&#x015F;tirme, ULAK Haberle&#x015F;me A.&#x015E;.,&#x0130;stanbul,T&#x00FC;rkiye"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Donan&#x0131;m Geli&#x015F;tirme, ULAK Haberle&#x015F;me A.&#x015E;.,&#x0130;stanbul,T&#x00FC;rkiye","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074182981","display_name":"M\u00fc\u015ftak E. Yal\u00e7\u0131n","orcid":"https://orcid.org/0000-0003-3377-2560"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M\u00fc\u015ftak Erhan Yal\u00e7in","raw_affiliation_strings":["Elektronik ve Haberle&#x015F;me M&#x00FC;h., &#x0130;stanbul Teknik &#x00DC;niversitesi,&#x0130;stanbul,T&#x00FC;rkiye"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Elektronik ve Haberle&#x015F;me M&#x00FC;h., &#x0130;stanbul Teknik &#x00DC;niversitesi,&#x0130;stanbul,T&#x00FC;rkiye","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.19735174,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10714","display_name":"Software-Defined Networks and 5G","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10400","display_name":"Network Security and Intrusion Detection","score":0.9865000247955322,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.78327876329422},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.7305552363395691},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6888076066970825},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6023921370506287},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5633261203765869},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.5358753204345703},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5278194546699524},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47541743516921997},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.4528530240058899},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.425862193107605},{"id":"https://openalex.org/keywords/network-processor","display_name":"Network processor","score":0.4229956865310669},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42052942514419556},{"id":"https://openalex.org/keywords/packet-processing","display_name":"Packet processing","score":0.4199499487876892},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.24466988444328308},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.13597476482391357},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11430701613426208}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.78327876329422},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.7305552363395691},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6888076066970825},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6023921370506287},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5633261203765869},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.5358753204345703},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5278194546699524},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47541743516921997},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.4528530240058899},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.425862193107605},{"id":"https://openalex.org/C74366991","wikidata":"https://www.wikidata.org/wiki/Q2755335","display_name":"Network processor","level":3,"score":0.4229956865310669},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42052942514419556},{"id":"https://openalex.org/C2779581428","wikidata":"https://www.wikidata.org/wiki/Q7122997","display_name":"Packet processing","level":3,"score":0.4199499487876892},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.24466988444328308},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.13597476482391357},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11430701613426208},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/siu49456.2020.9302072","is_oa":false,"landing_page_url":"https://doi.org/10.1109/siu49456.2020.9302072","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 28th Signal Processing and Communications Applications Conference (SIU)","raw_type":"proceedings-article"},{"id":"pmh:oai:polen.itu.edu.tr:11527/46233","is_oa":false,"landing_page_url":"https://hdl.handle.net/11527/46233","pdf_url":null,"source":{"id":"https://openalex.org/S4306400460","display_name":"Istanbul Technical University Academic Open Archive (Istanbul Technical University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I48912391","host_organization_name":"Istanbul Technical University","host_organization_lineage":["https://openalex.org/I48912391"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2102110274","https://openalex.org/W2133740603","https://openalex.org/W2587560295","https://openalex.org/W2795975079","https://openalex.org/W2890805660","https://openalex.org/W2896394395","https://openalex.org/W2900194769","https://openalex.org/W2905195012","https://openalex.org/W2953082982"],"related_works":["https://openalex.org/W2382274995","https://openalex.org/W1606574587","https://openalex.org/W1556003661","https://openalex.org/W2371307874","https://openalex.org/W2097731574","https://openalex.org/W1233822343","https://openalex.org/W2097595905","https://openalex.org/W4235315652","https://openalex.org/W1993620881","https://openalex.org/W2390663577"],"abstract_inverted_index":{"In":[0],"this":[1,37],"work,":[2],"a":[3],"novel":[4],"digital":[5],"hardware":[6],"architecture":[7,52],"is":[8,26,39],"proposed":[9,24,47,65],"in":[10,31,56],"order":[11,32],"to":[12,33],"accelerate":[13],"the":[14,54,59,64],"packet":[15],"classification":[16],"functions":[17],"of":[18],"network":[19],"router":[20],"on":[21,28],"hardware.":[22],"The":[23,46],"design":[25,38,44,48,66],"implemented":[27],"FPGA.":[29],"Besides,":[30],"obtain":[34],"maximum":[35],"performance,":[36],"optimized":[40],"by":[41],"using":[42],"several":[43],"techniques.":[45],"has":[49,67],"more":[50],"scalable":[51],"than":[53,72],"others":[55],"literature.":[57],"According":[58],"implementation":[60],"and":[61],"test":[62],"results,":[63],"%15":[68],"faster":[69],"clock":[70],"speed":[71],"similar":[73],"works.":[74]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
