{"id":"https://openalex.org/W4416751204","doi":"https://doi.org/10.1109/sips66314.2025.11261252","title":"Coarse-Grained ASIP Design for MIMO Sphere Decoding","display_name":"Coarse-Grained ASIP Design for MIMO Sphere Decoding","publication_year":2025,"publication_date":"2025-11-01","ids":{"openalex":"https://openalex.org/W4416751204","doi":"https://doi.org/10.1109/sips66314.2025.11261252"},"language":null,"primary_location":{"id":"doi:10.1109/sips66314.2025.11261252","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sips66314.2025.11261252","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Workshop on Signal Processing Systems (SiPS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101208707","display_name":"Junsu Heo","orcid":null},"institutions":[{"id":"https://openalex.org/I4210091929","display_name":"Konkuk University Medical Center","ror":"https://ror.org/00jcx1769","country_code":"KR","type":"healthcare","lineage":["https://openalex.org/I24062138","https://openalex.org/I4210091929"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Junsu Heo","raw_affiliation_strings":["Konkuk University,Department of Electrical and Electronics Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Konkuk University,Department of Electrical and Electronics Engineering","institution_ids":["https://openalex.org/I4210091929"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073511552","display_name":"Sinyoung Kim","orcid":"https://orcid.org/0000-0002-2609-8945"},"institutions":[{"id":"https://openalex.org/I4210091929","display_name":"Konkuk University Medical Center","ror":"https://ror.org/00jcx1769","country_code":"KR","type":"healthcare","lineage":["https://openalex.org/I24062138","https://openalex.org/I4210091929"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Shinyoung Kim","raw_affiliation_strings":["Konkuk University,Department of Electrical and Electronics Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Konkuk University,Department of Electrical and Electronics Engineering","institution_ids":["https://openalex.org/I4210091929"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088060647","display_name":"Sungkyung Park","orcid":"https://orcid.org/0000-0003-1171-5020"},"institutions":[{"id":"https://openalex.org/I4921948","display_name":"Pusan National University","ror":"https://ror.org/01an57a31","country_code":"KR","type":"education","lineage":["https://openalex.org/I4921948"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sungkyung Park","raw_affiliation_strings":["Pusan National University,Department of Electronics Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Pusan National University,Department of Electronics Engineering","institution_ids":["https://openalex.org/I4921948"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072573878","display_name":"Chester Sungchung Park","orcid":"https://orcid.org/0000-0003-2009-2814"},"institutions":[{"id":"https://openalex.org/I4210091929","display_name":"Konkuk University Medical Center","ror":"https://ror.org/00jcx1769","country_code":"KR","type":"healthcare","lineage":["https://openalex.org/I24062138","https://openalex.org/I4210091929"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Chester Sungchung Park","raw_affiliation_strings":["Konkuk University,Department of Electrical and Electronics Engineering"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Konkuk University,Department of Electrical and Electronics Engineering","institution_ids":["https://openalex.org/I4210091929"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.44440149,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.5699999928474426,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.5699999928474426,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.1736000031232834,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.04349999874830246,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5911999940872192},{"id":"https://openalex.org/keywords/application-specific-instruction-set-processor","display_name":"Application-specific instruction-set processor","score":0.582099974155426},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.5583999752998352},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5200999975204468},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4788999855518341},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.42969998717308044},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.413100004196167},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.40869998931884766},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.38760000467300415}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7426999807357788},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5911999940872192},{"id":"https://openalex.org/C201736964","wikidata":"https://www.wikidata.org/wiki/Q621583","display_name":"Application-specific instruction-set processor","level":3,"score":0.582099974155426},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.5583999752998352},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5200999975204468},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4805999994277954},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4788999855518341},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.42969998717308044},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.413100004196167},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.40869998931884766},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.40380001068115234},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.38760000467300415},{"id":"https://openalex.org/C207987634","wikidata":"https://www.wikidata.org/wiki/Q176862","display_name":"MIMO","level":3,"score":0.37770000100135803},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.357699990272522},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.352400004863739},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.33219999074935913},{"id":"https://openalex.org/C118993495","wikidata":"https://www.wikidata.org/wiki/Q5042828","display_name":"Electrical efficiency","level":3,"score":0.3319000005722046},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3287000060081482},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.3237999975681305},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3228999972343445},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3100999891757965},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.30649998784065247},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.29899999499320984},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.29840001463890076},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.29750001430511475},{"id":"https://openalex.org/C161911788","wikidata":"https://www.wikidata.org/wiki/Q190157","display_name":"Universal asynchronous receiver/transmitter","level":3,"score":0.2854999899864197},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.26600000262260437},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.26330000162124634},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.2605000138282776},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.25619998574256897},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.25060001015663147}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/sips66314.2025.11261252","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sips66314.2025.11261252","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Workshop on Signal Processing Systems (SiPS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320320671","display_name":"National Research Foundation","ror":"https://ror.org/05s0g1g46"},{"id":"https://openalex.org/F4320322202","display_name":"IC Design Education Center","ror":"https://ror.org/005v57z85"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1002369050","https://openalex.org/W1667950888","https://openalex.org/W1947927401","https://openalex.org/W1975286632","https://openalex.org/W1982692217","https://openalex.org/W2000519739","https://openalex.org/W2041647218","https://openalex.org/W2041756079","https://openalex.org/W2074072441","https://openalex.org/W2107080958","https://openalex.org/W2111124108","https://openalex.org/W2118425896","https://openalex.org/W2130664336","https://openalex.org/W2133475491","https://openalex.org/W2134295053","https://openalex.org/W2139317044","https://openalex.org/W2145842072","https://openalex.org/W2148978817","https://openalex.org/W2156787051","https://openalex.org/W2157961036","https://openalex.org/W2158439145","https://openalex.org/W2334821253","https://openalex.org/W2717766237","https://openalex.org/W2751306885","https://openalex.org/W2897534136","https://openalex.org/W2902132001","https://openalex.org/W2942894308","https://openalex.org/W2982293047","https://openalex.org/W3123366045","https://openalex.org/W3149849660","https://openalex.org/W3158552609","https://openalex.org/W3194490872"],"related_works":[],"abstract_inverted_index":{"Sphere":[0],"decoding":[1],"(SD),":[2],"a":[3,31],"key":[4],"enabler":[5],"for":[6],"nextgeneration":[7],"wireless":[8],"systems,":[9],"demands":[10],"not":[11],"only":[12],"implementation":[13],"efficiency":[14,38,46,144,162],"but":[15],"also":[16],"algorithm":[17],"flexibility.":[18],"A":[19],"novel":[20],"applicationspecific":[21],"instruction":[22,50,71,78],"set":[23,51,72],"processor":[24],"(ASIP),":[25],"FlexSD,":[26,48],"is":[27,52,100,128,153],"proposed":[28,157],"to":[29,61,102,165,169],"support":[30],"variety":[32],"of":[33,47,57,66,117,126,146],"SD":[34,64],"algorithms":[35,65],"with":[36,110],"high":[37],"under":[39],"varying":[40],"channel":[41,175],"conditions.":[42,176],"To":[43],"maximize":[44],"the":[45,49,55,62,89,91,97,104,111,122,131,156,160,170],"designed":[53],"on":[54,121],"basis":[56],"coarsegrained":[58],"operations":[59],"common":[60],"target":[63],"interest.":[67],"In":[68],"addition,":[69],"several":[70],"architecture":[73],"(ISA)":[74],"options":[75],"such":[76],"as":[77],"level":[79,107],"parallelism":[80],"(ILP)":[81],"and":[82,124],"hardware":[83],"resource":[84],"scheduling":[85],"are":[86],"proposed.":[87],"Given":[88],"ISA,":[90],"design":[92],"automation":[93],"tool":[94,113],"from":[95],"Synopsys,":[96],"ASIP":[98],"Designer,":[99],"utilized":[101],"generate":[103],"register":[105],"transfer":[106],"models":[108],"together":[109],"compiler":[112],"chains.":[114],"The":[115],"impact":[116],"each":[118],"ISA":[119,149],"option":[120],"performance":[123],"complexity":[125],"FlexSD":[127,140,158],"evaluated":[129],"using":[130],"28nm":[132],"CMOS":[133],"technology.":[134],"Logic":[135],"synthesis":[136],"results":[137],"show":[138],"that":[139,155],"accomplishes":[141],"an":[142],"area":[143],"improvement":[145],"2.35":[147],"through":[148],"optimizations.":[150],"Additionally,":[151],"it":[152],"shown":[154],"improves":[159],"power":[161],"by":[163],"up":[164],"$40":[166],"\\%$":[167],"compared":[168],"ASIC":[171],"counterpart":[172],"in":[173],"certain":[174]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-11-28T00:00:00"}