{"id":"https://openalex.org/W4308075506","doi":"https://doi.org/10.1109/sips55645.2022.9919203","title":"BERTPerf: Inference Latency Predictor for BERT on ARM big.LITTLE Multi-Core Processors","display_name":"BERTPerf: Inference Latency Predictor for BERT on ARM big.LITTLE Multi-Core Processors","publication_year":2022,"publication_date":"2022-11-02","ids":{"openalex":"https://openalex.org/W4308075506","doi":"https://doi.org/10.1109/sips55645.2022.9919203"},"language":"en","primary_location":{"id":"doi:10.1109/sips55645.2022.9919203","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sips55645.2022.9919203","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE Workshop on Signal Processing Systems (SiPS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110290848","display_name":"Mahmoud Abdel-Gawad","orcid":null},"institutions":[{"id":"https://openalex.org/I5023651","display_name":"McGill University","ror":"https://ror.org/01pxwe438","country_code":"CA","type":"education","lineage":["https://openalex.org/I5023651"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"M. Abdelgawad","raw_affiliation_strings":["McGill University,Department of Electrical and Computer Engineering,Montréal,QC,Canada"],"affiliations":[{"raw_affiliation_string":"McGill University,Department of Electrical and Computer Engineering,Montréal,QC,Canada","institution_ids":["https://openalex.org/I5023651"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056921752","display_name":"Seyyed Hasan Mozafari","orcid":"https://orcid.org/0000-0002-0360-1747"},"institutions":[{"id":"https://openalex.org/I5023651","display_name":"McGill University","ror":"https://ror.org/01pxwe438","country_code":"CA","type":"education","lineage":["https://openalex.org/I5023651"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"S. H. Mozafari","raw_affiliation_strings":["McGill University,Department of Electrical and Computer Engineering,Montréal,QC,Canada"],"affiliations":[{"raw_affiliation_string":"McGill University,Department of Electrical and Computer Engineering,Montréal,QC,Canada","institution_ids":["https://openalex.org/I5023651"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079264223","display_name":"James J. Clark","orcid":"https://orcid.org/0000-0002-4512-6171"},"institutions":[{"id":"https://openalex.org/I5023651","display_name":"McGill University","ror":"https://ror.org/01pxwe438","country_code":"CA","type":"education","lineage":["https://openalex.org/I5023651"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"J. J. Clark","raw_affiliation_strings":["McGill University,Department of Electrical and Computer Engineering,Montréal,QC,Canada"],"affiliations":[{"raw_affiliation_string":"McGill University,Department of Electrical and Computer Engineering,Montréal,QC,Canada","institution_ids":["https://openalex.org/I5023651"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034701871","display_name":"Brett H. Meyer","orcid":"https://orcid.org/0000-0002-6650-3298"},"institutions":[{"id":"https://openalex.org/I5023651","display_name":"McGill University","ror":"https://ror.org/01pxwe438","country_code":"CA","type":"education","lineage":["https://openalex.org/I5023651"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"B. H. Meyer","raw_affiliation_strings":["McGill University,Department of Electrical and Computer Engineering,Montréal,QC,Canada"],"affiliations":[{"raw_affiliation_string":"McGill University,Department of Electrical and Computer Engineering,Montréal,QC,Canada","institution_ids":["https://openalex.org/I5023651"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091600002","display_name":"Warren J. Gross","orcid":"https://orcid.org/0000-0002-6226-6037"},"institutions":[{"id":"https://openalex.org/I5023651","display_name":"McGill University","ror":"https://ror.org/01pxwe438","country_code":"CA","type":"education","lineage":["https://openalex.org/I5023651"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"W. J. Gross","raw_affiliation_strings":["McGill University,Department of Electrical and Computer Engineering,Montréal,QC,Canada"],"affiliations":[{"raw_affiliation_string":"McGill University,Department of Electrical and Computer Engineering,Montréal,QC,Canada","institution_ids":["https://openalex.org/I5023651"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5110290848"],"corresponding_institution_ids":["https://openalex.org/I5023651"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11839166,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9936000108718872,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10028","display_name":"Topic Modeling","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8329136967658997},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.7945926785469055},{"id":"https://openalex.org/keywords/inference","display_name":"Inference","score":0.7183021306991577},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.6081748604774475},{"id":"https://openalex.org/keywords/proxy","display_name":"Proxy (statistics)","score":0.5634506940841675},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.5547752976417542},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5528011918067932},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4474117159843445},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44237959384918213},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4366605281829834},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.43175217509269714},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.4273761808872223},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4115784764289856},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3658924698829651},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.16255027055740356},{"id":"https://openalex.org/keywords/machine-learning","display_name":"Machine learning","score":0.13865187764167786}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8329136967658997},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.7945926785469055},{"id":"https://openalex.org/C2776214188","wikidata":"https://www.wikidata.org/wiki/Q408386","display_name":"Inference","level":2,"score":0.7183021306991577},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.6081748604774475},{"id":"https://openalex.org/C2780148112","wikidata":"https://www.wikidata.org/wiki/Q1432581","display_name":"Proxy (statistics)","level":2,"score":0.5634506940841675},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.5547752976417542},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5528011918067932},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4474117159843445},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44237959384918213},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4366605281829834},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.43175217509269714},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.4273761808872223},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4115784764289856},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3658924698829651},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.16255027055740356},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.13865187764167786},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/sips55645.2022.9919203","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sips55645.2022.9919203","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE Workshop on Signal Processing Systems (SiPS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4386869637","https://openalex.org/W4387251174","https://openalex.org/W2169880332","https://openalex.org/W4242293745","https://openalex.org/W3009555776","https://openalex.org/W2099305970","https://openalex.org/W2052801483","https://openalex.org/W2087838646","https://openalex.org/W2164091863","https://openalex.org/W4292794827"],"abstract_inverted_index":{"Hardware-aware":[0],"Neural":[1],"Architecture":[2],"Search":[3],"(NAS)":[4],"and":[5,110,116,137],"mapping":[6],"&":[7],"scheduling":[8],"optimization":[9,74],"methods":[10],"are":[11],"being":[12],"used":[13],"to":[14,54,65,86,105,120,134,144],"find":[15],"efficient":[16],"implementations":[17],"of":[18,48,72,91,114],"computationally-intense":[19],"language":[20],"models":[21],"such":[22,42],"as":[23,43],"BERT.":[24],"This":[25],"requires":[26,138],"measuring":[27],"real":[28],"hardware":[29],"inference":[30,89],"latency:":[31],"good":[32],"design":[33],"decisions":[34],"simply":[35],"cannot":[36],"be":[37],"made":[38],"with":[39],"proxy":[40],"metrics":[41],"FLOPs":[44],"or":[45],"the":[46,51,70,88,103,112,127,135,148],"number":[47],"parameters.":[49],"However,":[50],"time":[52,90],"required":[53],"perform":[55],"on-device":[56,107,141],"latency":[57,100,108,122],"measurements":[58,142],"is":[59],"prohibitive":[60],"(e.g.,":[61],"a":[62,66,82],"few":[63,67],"days":[64],"weeks":[68],"over":[69],"course":[71],"an":[73],"run).":[75],"To":[76],"address":[77],"this,":[78],"we":[79],"present":[80],"BERTPerf,":[81],"low-cost,":[83],"highly-accurate":[84],"method":[85],"predict":[87],"BERT":[92],"on":[93],"ARM":[94],"big.LITTLE":[95],"multi-core":[96],"processors.":[97],"BERTPerf":[98,125],"exploits":[99],"patterns":[101],"at":[102,147],"layer-level":[104],"reduce":[106,121],"measurements,":[109],"captures":[111],"effect":[113],"caching":[115],"intermediate":[117],"tensor":[118],"allocations":[119],"prediction":[123,129,150],"error.":[124,151],"reduces":[126],"maximum":[128],"error":[130],"by":[131],"7\u201311%":[132],"compared":[133,143],"state-of-the-art,":[136],"75%":[139],"less":[140],"existing":[145],"work":[146],"same":[149]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}