{"id":"https://openalex.org/W2156407538","doi":"https://doi.org/10.1109/sips.2009.5336239","title":"Loop scheduling with memory access reduction under register constraints for DSP applications","display_name":"Loop scheduling with memory access reduction under register constraints for DSP applications","publication_year":2009,"publication_date":"2009-10-01","ids":{"openalex":"https://openalex.org/W2156407538","doi":"https://doi.org/10.1109/sips.2009.5336239","mag":"2156407538"},"language":"en","primary_location":{"id":"doi:10.1109/sips.2009.5336239","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sips.2009.5336239","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE Workshop on Signal Processing Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100377202","display_name":"Meng Wang","orcid":"https://orcid.org/0000-0002-8952-0840"},"institutions":[{"id":"https://openalex.org/I14243506","display_name":"Hong Kong Polytechnic University","ror":"https://ror.org/0030zas98","country_code":"HK","type":"education","lineage":["https://openalex.org/I14243506"]}],"countries":["HK"],"is_corresponding":true,"raw_author_name":"Meng Wang","raw_affiliation_strings":["Department of Computing, Hong Kong Polytechnic University, Hong Kong, China"],"affiliations":[{"raw_affiliation_string":"Department of Computing, Hong Kong Polytechnic University, Hong Kong, China","institution_ids":["https://openalex.org/I14243506"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100675843","display_name":"Duo Liu","orcid":"https://orcid.org/0000-0002-3040-2065"},"institutions":[{"id":"https://openalex.org/I14243506","display_name":"Hong Kong Polytechnic University","ror":"https://ror.org/0030zas98","country_code":"HK","type":"education","lineage":["https://openalex.org/I14243506"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Duo Liu","raw_affiliation_strings":["Department of Computing, Hong Kong Polytechnic University, Hong Kong, China"],"affiliations":[{"raw_affiliation_string":"Department of Computing, Hong Kong Polytechnic University, Hong Kong, China","institution_ids":["https://openalex.org/I14243506"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100364961","display_name":"Yi Wang","orcid":"https://orcid.org/0000-0002-5773-3817"},"institutions":[{"id":"https://openalex.org/I14243506","display_name":"Hong Kong Polytechnic University","ror":"https://ror.org/0030zas98","country_code":"HK","type":"education","lineage":["https://openalex.org/I14243506"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Yi Wang","raw_affiliation_strings":["Department of Computing, Hong Kong Polytechnic University, Hong Kong, China"],"affiliations":[{"raw_affiliation_string":"Department of Computing, Hong Kong Polytechnic University, Hong Kong, China","institution_ids":["https://openalex.org/I14243506"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101639532","display_name":"Zili Shao","orcid":"https://orcid.org/0000-0002-2173-2847"},"institutions":[{"id":"https://openalex.org/I14243506","display_name":"Hong Kong Polytechnic University","ror":"https://ror.org/0030zas98","country_code":"HK","type":"education","lineage":["https://openalex.org/I14243506"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Zili Shao","raw_affiliation_strings":["Department of Computing, Hong Kong Polytechnic University, Hong Kong, China"],"affiliations":[{"raw_affiliation_string":"Department of Computing, Hong Kong Polytechnic University, Hong Kong, China","institution_ids":["https://openalex.org/I14243506"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100377202"],"corresponding_institution_ids":["https://openalex.org/I14243506"],"apc_list":null,"apc_paid":null,"fwci":0.5276,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.69620128,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"139","last_page":"144"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.856589674949646},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.6903701424598694},{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.6589181423187256},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.5976589918136597},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.5799764394760132},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.563443660736084},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5474525094032288},{"id":"https://openalex.org/keywords/loop-unrolling","display_name":"Loop unrolling","score":0.5022850036621094},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.49610647559165955},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.47658535838127136},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4647336006164551},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.46361714601516724},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.4201759696006775},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.3617522120475769},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23683997988700867},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.2176264524459839},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1932103931903839},{"id":"https://openalex.org/keywords/two-level-scheduling","display_name":"Two-level scheduling","score":0.110984206199646}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.856589674949646},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.6903701424598694},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.6589181423187256},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.5976589918136597},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.5799764394760132},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.563443660736084},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5474525094032288},{"id":"https://openalex.org/C76970557","wikidata":"https://www.wikidata.org/wiki/Q1869750","display_name":"Loop unrolling","level":3,"score":0.5022850036621094},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.49610647559165955},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.47658535838127136},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4647336006164551},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.46361714601516724},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.4201759696006775},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.3617522120475769},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23683997988700867},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.2176264524459839},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1932103931903839},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.110984206199646},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/sips.2009.5336239","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sips.2009.5336239","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE Workshop on Signal Processing Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:ira.lib.polyu.edu.hk:10397/13325","is_oa":false,"landing_page_url":"http://hdl.handle.net/10397/13325","pdf_url":null,"source":{"id":"https://openalex.org/S4306400205","display_name":"PolyU Institutional Research Archive (Hong Kong Polytechnic University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I14243506","host_organization_name":"Hong Kong Polytechnic University","host_organization_lineage":["https://openalex.org/I14243506"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference Paper"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8600000143051147,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1686420892","https://openalex.org/W1982134186","https://openalex.org/W2006369600","https://openalex.org/W2007221644","https://openalex.org/W2016271465","https://openalex.org/W2021010544","https://openalex.org/W2044860726","https://openalex.org/W2092763781","https://openalex.org/W2106716060","https://openalex.org/W2156407538","https://openalex.org/W4238904016","https://openalex.org/W6637151178","https://openalex.org/W6683174534"],"related_works":["https://openalex.org/W1942542608","https://openalex.org/W2353958330","https://openalex.org/W2049342712","https://openalex.org/W2058188174","https://openalex.org/W2103250493","https://openalex.org/W2581286023","https://openalex.org/W2054117411","https://openalex.org/W2357256492","https://openalex.org/W3022819336","https://openalex.org/W1563688358"],"abstract_inverted_index":{"In":[0,19,43],"embedded":[1],"systems,":[2],"high-performance":[3],"DSP":[4,39],"needs":[5],"to":[6,34,50,64],"be":[7],"performed":[8],"not":[9],"only":[10],"with":[11,16,41],"high-data":[12],"throughput":[13],"but":[14],"also":[15],"low-power":[17],"consumption.":[18],"this":[20],"paper,":[21],"we":[22,46],"propose":[23],"an":[24],"effective":[25],"scheduling":[26],"framework,":[27,45],"MARLS":[28],"(Memory":[29],"Access":[30],"Reduction":[31],"Loop":[32],"Scheduling),":[33],"reduce":[35],"memory":[36,107],"accesses":[37],"for":[38],"applications":[40],"loops.":[42],"the":[44,73,89,104],"generate":[47],"register":[48,66],"operations":[49,58],"replace":[51],"redundant":[52],"load":[53],"operations,":[54],"and":[55,76,86],"schedule":[56],"these":[57],"while":[59],"allocating":[60],"available":[61],"physical":[62],"registers":[63],"their":[65],"operands.":[67],"We":[68],"implement":[69],"our":[70,100],"technique":[71,101],"into":[72],"Trimaran":[74],"compiler":[75],"conduct":[77],"experiments":[78],"using":[79],"a":[80],"set":[81],"of":[82,93,106],"benchmarks":[83],"from":[84],"DSPstone":[85],"MiBench":[87],"on":[88],"cycle-accurate":[90],"VLIW":[91],"simulator":[92],"Trimaran.":[94],"The":[95],"experimental":[96],"results":[97],"show":[98],"that":[99],"significantly":[102],"reduces":[103],"number":[105],"accesses.":[108]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}