{"id":"https://openalex.org/W2888721704","doi":"https://doi.org/10.1109/sies.2018.8442100","title":"Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu","display_name":"Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu","publication_year":2018,"publication_date":"2018-06-01","ids":{"openalex":"https://openalex.org/W2888721704","doi":"https://doi.org/10.1109/sies.2018.8442100","mag":"2888721704"},"language":"en","primary_location":{"id":"doi:10.1109/sies.2018.8442100","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sies.2018.8442100","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028238740","display_name":"Christian Fibich","orcid":"https://orcid.org/0000-0001-8499-1507"},"institutions":[{"id":"https://openalex.org/I121760703","display_name":"University of Applied Sciences Technikum Wien","ror":"https://ror.org/04jsx0x49","country_code":"AT","type":"education","lineage":["https://openalex.org/I121760703"]}],"countries":["AT"],"is_corresponding":true,"raw_author_name":"Christian Fibich","raw_affiliation_strings":["Department of Embedded Systems, University of Applied Sciences Technikum Wien, Wien, Austria"],"affiliations":[{"raw_affiliation_string":"Department of Embedded Systems, University of Applied Sciences Technikum Wien, Wien, Austria","institution_ids":["https://openalex.org/I121760703"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059943175","display_name":"Stefan Tauner","orcid":"https://orcid.org/0000-0002-8806-7730"},"institutions":[{"id":"https://openalex.org/I121760703","display_name":"University of Applied Sciences Technikum Wien","ror":"https://ror.org/04jsx0x49","country_code":"AT","type":"education","lineage":["https://openalex.org/I121760703"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Stefan Tauner","raw_affiliation_strings":["Department of Embedded Systems, University of Applied Sciences Technikum Wien, Wien, Austria"],"affiliations":[{"raw_affiliation_string":"Department of Embedded Systems, University of Applied Sciences Technikum Wien, Wien, Austria","institution_ids":["https://openalex.org/I121760703"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089848700","display_name":"Peter R\u00f6ssler","orcid":"https://orcid.org/0000-0002-0557-229X"},"institutions":[{"id":"https://openalex.org/I121760703","display_name":"University of Applied Sciences Technikum Wien","ror":"https://ror.org/04jsx0x49","country_code":"AT","type":"education","lineage":["https://openalex.org/I121760703"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Peter Rossler","raw_affiliation_strings":["Department of Embedded Systems, University of Applied Sciences Technikum Wien, Wien, Austria"],"affiliations":[{"raw_affiliation_string":"Department of Embedded Systems, University of Applied Sciences Technikum Wien, Wien, Austria","institution_ids":["https://openalex.org/I121760703"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028034207","display_name":"Martin Horauer","orcid":"https://orcid.org/0000-0001-6835-0662"},"institutions":[{"id":"https://openalex.org/I121760703","display_name":"University of Applied Sciences Technikum Wien","ror":"https://ror.org/04jsx0x49","country_code":"AT","type":"education","lineage":["https://openalex.org/I121760703"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Martin Horauer","raw_affiliation_strings":["Department of Embedded Systems, University of Applied Sciences Technikum Wien, Wien, Austria"],"affiliations":[{"raw_affiliation_string":"Department of Embedded Systems, University of Applied Sciences Technikum Wien, Wien, Austria","institution_ids":["https://openalex.org/I121760703"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039631327","display_name":"Herbert Taucher","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127033","display_name":"Siemens (Austria)","ror":"https://ror.org/03794w632","country_code":"AT","type":"company","lineage":["https://openalex.org/I1325886976","https://openalex.org/I4210127033"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Herbert Taucher","raw_affiliation_strings":["Research Group Electronic Design Corp. Tech, Siemens AG Austria, Wien, Austria"],"affiliations":[{"raw_affiliation_string":"Research Group Electronic Design Corp. Tech, Siemens AG Austria, Wien, Austria","institution_ids":["https://openalex.org/I4210127033"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068808023","display_name":"Martin Matschnig","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127033","display_name":"Siemens (Austria)","ror":"https://ror.org/03794w632","country_code":"AT","type":"company","lineage":["https://openalex.org/I1325886976","https://openalex.org/I4210127033"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Martin Matschnig","raw_affiliation_strings":["Research Group Electronic Design Corp. Tech, Siemens AG Austria, Wien, Austria"],"affiliations":[{"raw_affiliation_string":"Research Group Electronic Design Corp. Tech, Siemens AG Austria, Wien, Austria","institution_ids":["https://openalex.org/I4210127033"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5028238740"],"corresponding_institution_ids":["https://openalex.org/I121760703"],"apc_list":null,"apc_paid":null,"fwci":1.2934,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.79295522,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.8171195983886719},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7762935161590576},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7131638526916504},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5941327810287476},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5026798248291016},{"id":"https://openalex.org/keywords/source-code","display_name":"Source code","score":0.4663001596927643},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4500921666622162},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4080839455127716},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.12626948952674866},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.12101611495018005},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11464312672615051},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10805362462997437}],"concepts":[{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.8171195983886719},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7762935161590576},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7131638526916504},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5941327810287476},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5026798248291016},{"id":"https://openalex.org/C43126263","wikidata":"https://www.wikidata.org/wiki/Q128751","display_name":"Source code","level":2,"score":0.4663001596927643},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4500921666622162},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4080839455127716},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.12626948952674866},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.12101611495018005},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11464312672615051},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10805362462997437}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/sies.2018.8442100","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sies.2018.8442100","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5600000023841858,"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320320273","display_name":"University of Cambridge","ror":"https://ror.org/013meh722"},{"id":"https://openalex.org/F4320323591","display_name":"Christian Doppler Forschungsgesellschaft","ror":"https://ror.org/00mv8h305"},{"id":"https://openalex.org/F4320327593","display_name":"Bundesministerium f\u00fcr Digitalisierung und Wirtschaftsstandort","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1604677972","https://openalex.org/W1995207020","https://openalex.org/W2034270503","https://openalex.org/W2057807751","https://openalex.org/W2133059825","https://openalex.org/W2343695530","https://openalex.org/W2482246557"],"related_works":["https://openalex.org/W2612099726","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W2160632767","https://openalex.org/W1608572506","https://openalex.org/W2135482679","https://openalex.org/W2035070505","https://openalex.org/W2000188956","https://openalex.org/W1973862904","https://openalex.org/W181593118"],"abstract_inverted_index":{"High-Ievel":[0],"synthesis":[1,9,34],"promises":[2],"a":[3,26,49],"boost":[4],"in":[5,45],"productivity":[6],"by":[7],"enabling":[8],"of":[10,16,29,65],"low-level":[11],"electronic":[12],"circuit":[13],"descriptions":[14],"out":[15],"high-level":[17,33],"source":[18,55],"code.":[19],"In":[20],"this":[21],"work-in-progress":[22],"paper":[23],"we":[24],"present":[25],"preliminary":[27],"evaluation":[28],"two":[30],"freely":[31],"available":[32],"tools":[35],"using":[36],"four":[37],"case":[38,60],"studies.":[39],"We":[40],"describe":[41],"the":[42,63,66],"steps":[43],"required":[44],"order":[46],"to":[47],"obtain":[48],"synthesizable":[50],"FPGA":[51],"design":[52],"from":[53],"C":[54],"code":[56],"for":[57],"each":[58],"use":[59],"and":[61],"discuss":[62],"performance":[64],"resulting":[67],"hardware":[68],"implementations.":[69]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2}],"updated_date":"2026-03-04T09:10:02.777135","created_date":"2025-10-10T00:00:00"}
