{"id":"https://openalex.org/W2468031566","doi":"https://doi.org/10.1109/sies.2016.7509424","title":"Automated FPGA implementations of BIP designs","display_name":"Automated FPGA implementations of BIP designs","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2468031566","doi":"https://doi.org/10.1109/sies.2016.7509424","mag":"2468031566"},"language":"en","primary_location":{"id":"doi:10.1109/sies.2016.7509424","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sies.2016.7509424","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012477886","display_name":"Maya H. Safieddine","orcid":"https://orcid.org/0000-0002-1674-9628"},"institutions":[{"id":"https://openalex.org/I98635879","display_name":"American University of Beirut","ror":"https://ror.org/04pznsd21","country_code":"LB","type":"education","lineage":["https://openalex.org/I98635879"]}],"countries":["LB"],"is_corresponding":true,"raw_author_name":"Maya H. Safieddine","raw_affiliation_strings":["American University of Beirut"],"affiliations":[{"raw_affiliation_string":"American University of Beirut","institution_ids":["https://openalex.org/I98635879"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010806171","display_name":"Fadi A. Zaraket","orcid":"https://orcid.org/0000-0001-5909-6375"},"institutions":[{"id":"https://openalex.org/I98635879","display_name":"American University of Beirut","ror":"https://ror.org/04pznsd21","country_code":"LB","type":"education","lineage":["https://openalex.org/I98635879"]}],"countries":["LB"],"is_corresponding":false,"raw_author_name":"Fadi A. Zaraket","raw_affiliation_strings":["American University of Beirut"],"affiliations":[{"raw_affiliation_string":"American University of Beirut","institution_ids":["https://openalex.org/I98635879"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088676304","display_name":"Mohamad Jaber","orcid":"https://orcid.org/0000-0003-2457-9742"},"institutions":[{"id":"https://openalex.org/I98635879","display_name":"American University of Beirut","ror":"https://ror.org/04pznsd21","country_code":"LB","type":"education","lineage":["https://openalex.org/I98635879"]}],"countries":["LB"],"is_corresponding":false,"raw_author_name":"Mohamad Jaber","raw_affiliation_strings":["American University of Beirut"],"affiliations":[{"raw_affiliation_string":"American University of Beirut","institution_ids":["https://openalex.org/I98635879"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071376756","display_name":"Rouwaida Kanj","orcid":"https://orcid.org/0000-0002-3519-2917"},"institutions":[{"id":"https://openalex.org/I98635879","display_name":"American University of Beirut","ror":"https://ror.org/04pznsd21","country_code":"LB","type":"education","lineage":["https://openalex.org/I98635879"]}],"countries":["LB"],"is_corresponding":false,"raw_author_name":"Rouwaida Kanj","raw_affiliation_strings":["American University of Beirut"],"affiliations":[{"raw_affiliation_string":"American University of Beirut","institution_ids":["https://openalex.org/I98635879"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112793176","display_name":"Mazen A. R. Saghir","orcid":null},"institutions":[{"id":"https://openalex.org/I98635879","display_name":"American University of Beirut","ror":"https://ror.org/04pznsd21","country_code":"LB","type":"education","lineage":["https://openalex.org/I98635879"]}],"countries":["LB"],"is_corresponding":false,"raw_author_name":"Mazen A. R. Saghir","raw_affiliation_strings":["American University of Beirut"],"affiliations":[{"raw_affiliation_string":"American University of Beirut","institution_ids":["https://openalex.org/I98635879"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5012477886"],"corresponding_institution_ids":["https://openalex.org/I98635879"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06301792,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"8146","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.887240469455719},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7485353946685791},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7092944979667664},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6999114155769348},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.6433577537536621},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5818328857421875},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.5494831800460815},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5163922905921936},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.43647122383117676},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43356242775917053},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4252469539642334},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4189104735851288},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2645169794559479},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11793670058250427},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.06758180260658264}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.887240469455719},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7485353946685791},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7092944979667664},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6999114155769348},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.6433577537536621},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5818328857421875},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.5494831800460815},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5163922905921936},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.43647122383117676},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43356242775917053},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4252469539642334},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4189104735851288},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2645169794559479},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11793670058250427},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.06758180260658264},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/sies.2016.7509424","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sies.2016.7509424","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5400000214576721,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1554303980","https://openalex.org/W1575369083","https://openalex.org/W1588172920","https://openalex.org/W1890639535","https://openalex.org/W1964587130","https://openalex.org/W1992160941","https://openalex.org/W2044025886","https://openalex.org/W2048903680","https://openalex.org/W2050616463","https://openalex.org/W2076997912","https://openalex.org/W2134545467","https://openalex.org/W2140321074","https://openalex.org/W2156420848","https://openalex.org/W2167336741","https://openalex.org/W2293100135","https://openalex.org/W2962762993","https://openalex.org/W4244062578","https://openalex.org/W6634364008","https://openalex.org/W6825444808"],"related_works":["https://openalex.org/W2535403365","https://openalex.org/W1486911645","https://openalex.org/W3147061323","https://openalex.org/W2118796996","https://openalex.org/W2113648965","https://openalex.org/W2091330445","https://openalex.org/W2365114398","https://openalex.org/W2243815476","https://openalex.org/W3128899411","https://openalex.org/W2476941693"],"abstract_inverted_index":{"Embedded":[0],"system":[1],"designs":[2],"have":[3],"IP":[4,41],"components":[5,42],"that":[6,55,90],"each":[7],"may":[8],"be":[9,44,184],"implemented":[10,110,122],"as":[11,156],"either":[12],"software":[13,149,201],"or":[14],"realtime":[15],"accelerated":[16],"hardware":[17,30],"depending":[18],"on":[19,46,123,167,204],"the":[20,23,47,72,85,103,116,128,132,139,148,152,168,190,199],"logic":[21],"and":[22,39,70,77,113,134,145,162,175,195],"available":[24],"resources.":[25],"FPGA":[26,49,98,179],"implementations":[27,31],"are":[28,37],"desirable":[29],"for":[32,213],"embedded":[33,60],"systems":[34,61],"since":[35],"they":[36],"reconfigurable":[38],"several":[40],"can":[43],"deployed":[45],"same":[48],"board.":[50],"BIP":[51,93,153,169,174,193],"is":[52,181],"a":[53,65,92,106,119],"framework":[54],"facilitates":[56],"correct-by-construction":[57],"design":[58,68,88,94,104,129,154,215],"of":[59,74,143,147,151],"by":[62],"leveraging":[63],"(1)":[64],"component":[66],"based":[67],"paradigm":[69],"(2)":[71],"separation":[73],"behavior,":[75],"interaction,":[76],"priority":[78],"concerns.":[79],"In":[80],"this":[81],"paper,":[82],"we":[83],"present":[84],"first":[86,101],"automated":[87],"flow":[89,130],"takes":[91],"into":[95,105,118],"an":[96,124],"efficient":[97],"implementation.":[99],"We":[100,126,137,165],"transform":[102],"one":[107],"loop":[108],"program":[109,117],"in":[111,141],"C/C++":[112,163,200],"then":[114],"take":[115],"sequential":[120],"circuit":[121],"FPGA.":[125],"evaluate":[127],"with":[131],"ATM":[133],"Quorom":[135],"designs.":[136],"compare":[138],"results":[140],"terms":[142],"efficiency":[144],"performance":[146,211],"realizations":[150],"such":[155],"regular":[157,173],"BIP,":[158,161],"enhanced":[159,191],"flat":[160,176,192],"simulations.":[164],"rely":[166],"engine":[170],"to":[171,183],"simulate":[172],"BIP.":[177],"The":[178],"implementation":[180,194],"shown":[182],"at":[185],"least":[186],"16x-30x":[187],"faster":[188,197],"than":[189,198],"7x-10x":[196],"realization":[202],"running":[203],"state-of-the-art":[205],"processors.":[206],"Our":[207],"experiments":[208],"show":[209],"higher":[210],"improvement":[212],"larger":[214],"systems.":[216]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
