{"id":"https://openalex.org/W3205304972","doi":"https://doi.org/10.1109/seeda-cecnsm53056.2021.9566219","title":"An Optimization-Based Approach for Analog Circuit Technology Migration","display_name":"An Optimization-Based Approach for Analog Circuit Technology Migration","publication_year":2021,"publication_date":"2021-09-24","ids":{"openalex":"https://openalex.org/W3205304972","doi":"https://doi.org/10.1109/seeda-cecnsm53056.2021.9566219","mag":"3205304972"},"language":"en","primary_location":{"id":"doi:10.1109/seeda-cecnsm53056.2021.9566219","is_oa":false,"landing_page_url":"https://doi.org/10.1109/seeda-cecnsm53056.2021.9566219","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 6th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035761905","display_name":"\u039aostas Touloupas","orcid":"https://orcid.org/0000-0002-9266-6146"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Kostas Touloupas","raw_affiliation_strings":["National Technical University of Athens, Zografou, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Technical University of Athens, Zografou, Greece","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013213336","display_name":"Paul P. Sotiriadis","orcid":"https://orcid.org/0000-0001-6030-4645"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Paul Peter Sotiriadis","raw_affiliation_strings":["National Technical University of Athens, Zografou, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Technical University of Athens, Zografou, Greece","institution_ids":["https://openalex.org/I174458059"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I174458059"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15140291,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10848","display_name":"Advanced Multi-Objective Optimization Algorithms","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.8331388235092163},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6969504356384277},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.6461066007614136},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.6039473414421082},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.5151585340499878},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47889629006385803},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4658931493759155},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4626871347427368},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.45479777455329895},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43203017115592957},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3329067826271057},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3321060538291931},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.33062443137168884},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24088969826698303},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1924411952495575},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.1553577184677124},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11075782775878906}],"concepts":[{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.8331388235092163},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6969504356384277},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.6461066007614136},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.6039473414421082},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.5151585340499878},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47889629006385803},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4658931493759155},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4626871347427368},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.45479777455329895},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43203017115592957},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3329067826271057},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3321060538291931},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.33062443137168884},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24088969826698303},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1924411952495575},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.1553577184677124},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11075782775878906},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/seeda-cecnsm53056.2021.9566219","is_oa":false,"landing_page_url":"https://doi.org/10.1109/seeda-cecnsm53056.2021.9566219","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 6th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/10","score":0.7099999785423279,"display_name":"Reduced inequalities"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"},{"id":"https://openalex.org/F4320321916","display_name":"State Scholarships Foundation","ror":"https://ror.org/023z3dm33"},{"id":"https://openalex.org/F4320338080","display_name":"European Social Fund","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1746819321","https://openalex.org/W1872183006","https://openalex.org/W2030422718","https://openalex.org/W2033168046","https://openalex.org/W2055936709","https://openalex.org/W2085737637","https://openalex.org/W2144133630","https://openalex.org/W2145479420","https://openalex.org/W2192203593","https://openalex.org/W2751298281","https://openalex.org/W2799181865","https://openalex.org/W2969999645","https://openalex.org/W2978512279","https://openalex.org/W3026476728","https://openalex.org/W4211049957","https://openalex.org/W6750868688","https://openalex.org/W6766900132"],"related_works":["https://openalex.org/W3154683910","https://openalex.org/W1846734616","https://openalex.org/W3134543635","https://openalex.org/W2359532622","https://openalex.org/W2921318524","https://openalex.org/W2377571686","https://openalex.org/W4380988671","https://openalex.org/W4318953393","https://openalex.org/W2122222688","https://openalex.org/W1933057227"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"a":[3,21,28,36,45,49,57,98,102],"new":[4,58],"approach":[5,19,85],"for":[6,61],"automatic":[7],"technology":[8,42,51],"migration":[9],"of":[10,80],"analog":[11],"Integrated":[12],"Circuits":[13],"(ICs)":[14],"is":[15,86],"described.":[16],"The":[17,83],"proposed":[18,84],"uses":[20],"software":[22],"interface":[23],"between":[24],"commercial":[25],"simulators":[26],"and":[27,68],"Bayesian":[29],"Optimization":[30],"(BO)":[31],"algorithm":[32],"to":[33,66,101],"automatically":[34],"size":[35],"fixed":[37],"topology":[38],"in":[39,48,73],"the":[40,77,81],"target":[41],"node,":[43],"given":[44],"sized":[46],"schematic":[47],"source":[50],"as":[52],"golden":[53],"standard.":[54],"By":[55],"using":[56],"acquisition":[59],"function":[60],"BO,":[62],"we":[63],"are":[64],"able":[65],"simulate":[67],"examine":[69],"multiple":[70],"candidate":[71],"solutions":[72],"parallel,":[74],"thereby":[75],"reducing":[76],"total":[78],"runtime":[79],"procedure.":[82],"demonstrated":[87],"on":[88],"two":[89],"real":[90],"world":[91],"circuits,":[92],"by":[93],"migrating":[94],"their":[95],"schematics":[96],"from":[97],"TSMC":[99,103],"90nm":[100],"40nm":[104],"technology.":[105]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}