{"id":"https://openalex.org/W4247741062","doi":"https://doi.org/10.1109/sc.2008.5213921","title":"Programming the Intel 80-core network-on-a-chip Terascale Processor","display_name":"Programming the Intel 80-core network-on-a-chip Terascale Processor","publication_year":2008,"publication_date":"2008-11-01","ids":{"openalex":"https://openalex.org/W4247741062","doi":"https://doi.org/10.1109/sc.2008.5213921"},"language":"en","primary_location":{"id":"doi:10.1109/sc.2008.5213921","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sc.2008.5213921","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 SC - International Conference for High Performance Computing, Networking, Storage and Analysis","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048097160","display_name":"Timothy G. Mattson","orcid":"https://orcid.org/0000-0002-6106-8717"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Timothy G. Mattson","raw_affiliation_strings":["Intel Corporation, Dupont, WA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Dupont, WA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066479345","display_name":"Rob Van der Wijngaart","orcid":"https://orcid.org/0009-0008-4609-6403"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rob Van der Wijngaart","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039743878","display_name":"Michael Frumkin","orcid":null},"institutions":[{"id":"https://openalex.org/I1291425158","display_name":"Google (United States)","ror":"https://ror.org/00njsd438","country_code":"US","type":"company","lineage":["https://openalex.org/I1291425158","https://openalex.org/I4210128969"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Frumkin","raw_affiliation_strings":["Google Japan, Inc., Mountain View, CA, USA"],"affiliations":[{"raw_affiliation_string":"Google Japan, Inc., Mountain View, CA, USA","institution_ids":["https://openalex.org/I1291425158"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5048097160"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":4.8525,"has_fulltext":false,"cited_by_count":43,"citation_normalized_percentile":{"value":0.95535993,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"11"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8472375273704529},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.676041841506958},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5414239764213562},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5154805779457092},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.4876305162906647},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.482552707195282},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4821698069572449},{"id":"https://openalex.org/keywords/stencil","display_name":"Stencil","score":0.46628686785697937},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4622715413570404},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.43320879340171814},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40295320749282837},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3697732388973236},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10254624485969543}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8472375273704529},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.676041841506958},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5414239764213562},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5154805779457092},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.4876305162906647},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.482552707195282},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4821698069572449},{"id":"https://openalex.org/C76752949","wikidata":"https://www.wikidata.org/wiki/Q7607499","display_name":"Stencil","level":2,"score":0.46628686785697937},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4622715413570404},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.43320879340171814},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40295320749282837},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3697732388973236},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10254624485969543},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/sc.2008.5213921","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sc.2008.5213921","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 SC - International Conference for High Performance Computing, Networking, Storage and Analysis","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1979502974","https://openalex.org/W2026014559","https://openalex.org/W2159747318","https://openalex.org/W3140261852"],"related_works":["https://openalex.org/W3105129168","https://openalex.org/W2804920739","https://openalex.org/W4316371992","https://openalex.org/W2186216222","https://openalex.org/W2392765154","https://openalex.org/W2008005532","https://openalex.org/W1971603802","https://openalex.org/W2564509292","https://openalex.org/W1970479385","https://openalex.org/W2048275941"],"abstract_inverted_index":{"Intel's":[0],"80-core":[1,87],"terascale":[2,88],"processor":[3,89],"was":[4,21],"the":[5,12,19,59,64,69,73,78,83,86,93,99,102,105,109,121],"first":[6],"generally":[7],"programmable":[8],"microprocessor":[9],"to":[10,22,76],"break":[11],"Teraflops":[13],"barrier.":[14],"The":[15,56],"primary":[16],"goal":[17],"for":[18,41,108,131],"chip":[20],"study":[23],"power":[24],"management":[25],"and":[26,111,127],"on-die":[27],"communication":[28],"technologies.":[29],"When":[30],"announced":[31],"in":[32],"2007,":[33],"it":[34,129],"received":[35],"a":[36,43],"great":[37],"deal":[38],"of":[39],"attention":[40],"running":[42],"stencil":[44],"kernel":[45],"at":[46],"1.0":[47],"single":[48],"precision":[49],"TFLOPS":[50],"while":[51],"using":[52],"only":[53],"97":[54],"Watts.":[55],"literature":[57,84],"about":[58,68],"chip,":[60,110],"however,":[61],"focused":[62],"on":[63,85],"hardware,":[65],"saying":[66],"little":[67],"software":[70,95],"environment":[71],"or":[72],"kernels":[74,106],"used":[75],"evaluate":[77],"chip.":[79],"This":[80],"paper":[81],"completes":[82],"by":[90,119],"fully":[91],"defining":[92],"chip's":[94],"environment.":[96],"We":[97,117],"describe":[98],"instruction":[100],"set,":[101],"programming":[103,114],"environment,":[104],"written":[107],"our":[112],"experiences":[113],"this":[115,125],"microprocessor.":[116],"close":[118],"discussing":[120],"lessons":[122],"learned":[123],"from":[124],"project":[126],"what":[128],"implies":[130],"future":[132],"message":[133],"passing,":[134],"network-on-a-chip":[135],"processors.":[136]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":10}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
