{"id":"https://openalex.org/W4415744101","doi":"https://doi.org/10.1109/sbcci66862.2025.11218675","title":"Approximate Adders for Efficient Circuits: Advantages and Limitations Compared to RCA","display_name":"Approximate Adders for Efficient Circuits: Advantages and Limitations Compared to RCA","publication_year":2025,"publication_date":"2025-08-25","ids":{"openalex":"https://openalex.org/W4415744101","doi":"https://doi.org/10.1109/sbcci66862.2025.11218675"},"language":null,"primary_location":{"id":"doi:10.1109/sbcci66862.2025.11218675","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci66862.2025.11218675","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 38th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5105100643","display_name":"V\u00edtor de Melo Mandowski","orcid":"https://orcid.org/0009-0005-5257-8407"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"V\u00edtor De M. Mandowski","raw_affiliation_strings":["Federal University of Pelotas (UFPel),Graduate Program in Computer Science (PPGC),Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Pelotas (UFPel),Graduate Program in Computer Science (PPGC),Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018449089","display_name":"Pedro T. L. Pereira","orcid":"https://orcid.org/0000-0001-5231-3963"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Pedro T. L. Pereira","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS),Graduate Program on Microelectronics (PGMicro),Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS),Graduate Program on Microelectronics (PGMicro),Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062131940","display_name":"Paulo F. Butzen","orcid":"https://orcid.org/0000-0003-1587-7596"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Paulo F. Butzen","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS),Graduate Program on Microelectronics (PGMicro),Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS),Graduate Program on Microelectronics (PGMicro),Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046426137","display_name":"S\u00e9rgio Bampi","orcid":"https://orcid.org/0000-0002-9018-6309"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Sergio Bampi","raw_affiliation_strings":["Federal University of Rio Grande do Sul (UFRGS),Graduate Program on Microelectronics (PGMicro),Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul (UFRGS),Graduate Program on Microelectronics (PGMicro),Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014303947","display_name":"Leomar S. da Rosa","orcid":"https://orcid.org/0000-0002-7150-5685"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Leomar S. Da R. J\u00fanior","raw_affiliation_strings":["Federal University of Pelotas (UFPel),Graduate Program in Computer Science (PPGC),Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Pelotas (UFPel),Graduate Program in Computer Science (PPGC),Brazil","institution_ids":["https://openalex.org/I169248161"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4626,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.69311808,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.781000018119812,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.781000018119812,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.13030000030994415,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.042399998754262924,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9758999943733215},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.8165000081062317},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.8070999979972839},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.6779000163078308},{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.5432999730110168},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.44369998574256897},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4431999921798706},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.41760000586509705}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9758999943733215},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.8165000081062317},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.8070999979972839},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.6779000163078308},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.5432999730110168},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5428000092506409},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5230000019073486},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.44369998574256897},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4431999921798706},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.41760000586509705},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41130000352859497},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.3986999988555908},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.39629998803138733},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3937000036239624},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.32600000500679016},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.32580000162124634},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3255000114440918},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.3206000030040741},{"id":"https://openalex.org/C106195933","wikidata":"https://www.wikidata.org/wiki/Q7847935","display_name":"Truncation (statistics)","level":2,"score":0.30640000104904175},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.29600000381469727},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.2939999997615814},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.2888000011444092},{"id":"https://openalex.org/C2776299755","wikidata":"https://www.wikidata.org/wiki/Q432449","display_name":"Carry (investment)","level":2,"score":0.28790000081062317},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.28630000352859497},{"id":"https://openalex.org/C2779599953","wikidata":"https://www.wikidata.org/wiki/Q1776117","display_name":"Ripple","level":3,"score":0.26649999618530273}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/sbcci66862.2025.11218675","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci66862.2025.11218675","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 38th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2002797709","https://openalex.org/W2079986413","https://openalex.org/W2135089667","https://openalex.org/W2768707373","https://openalex.org/W3141620748","https://openalex.org/W3188623054","https://openalex.org/W4366374086","https://openalex.org/W4381329078","https://openalex.org/W4385730899","https://openalex.org/W4389941658","https://openalex.org/W4406219903"],"related_works":[],"abstract_inverted_index":{"The":[0,90],"ripple":[1],"carry":[2,29],"adder":[3,70],"(RCA)":[4],"is":[5,21,92],"the":[6,11,22,27,38,61,74,98,115],"simplest":[7],"N-bit":[8],"adder,":[9],"with":[10],"lowest":[12],"circuit":[13,51,99,135],"area":[14,136],"and":[15,53,63,82,87,105,118,123,137,148],"power":[16,54,101],"consumption.":[17,55],"Its":[18],"main":[19],"drawback":[20],"high":[23],"propagation":[24,49,103,138],"delay":[25,139],"in":[26,80],"critical":[28],"path,":[30],"through":[31],"N":[32],"full":[33],"adders.":[34],"In":[35],"error-tolerant":[36],"applications,":[37],"use":[39],"of":[40,65,68,108],"approximate":[41,69],"adders":[42],"can":[43],"bring":[44],"significant":[45],"benefits,":[46],"including":[47],"reduced":[48],"delay,":[50,104],"area,":[52,100],"This":[56],"work":[57],"aims":[58],"to":[59,73,84,141],"analyze":[60],"advantages":[62],"disadvantages":[64],"a":[66],"set":[67],"topologies":[71,77],"compared":[72,140],"RCA.":[75],"Different":[76],"are":[78],"described":[79],"Verilog":[81],"subjected":[83],"both":[85],"logic":[86],"physical":[88],"synthesis.":[89],"comparison":[91],"based":[93],"on":[94],"metrics":[95],"such":[96],"as":[97],"consumption,":[102],"error":[106,131],"rate":[107],"each":[109],"approach.":[110],"Our":[111],"experiment":[112],"shows":[113],"that":[114],"Lower-Part":[116,124,144,149],"XOR":[117],"OR":[119,125],"Gating":[120,126],"Adder":[121,127,146,151],"(LXOA)":[122],"(LOA)":[128],"exhibit":[129],"lower":[130],"rates":[132],"but":[133],"higher":[134],"techniques":[142],"like":[143],"Truncation":[145],"(LTA)":[147],"Copy":[150],"(LCA).":[152]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-31T00:00:00"}
