{"id":"https://openalex.org/W4415744218","doi":"https://doi.org/10.1109/sbcci66862.2025.11218646","title":"Novel Simplified Analog Neuron in CMOS Technology with Digital Weights","display_name":"Novel Simplified Analog Neuron in CMOS Technology with Digital Weights","publication_year":2025,"publication_date":"2025-08-25","ids":{"openalex":"https://openalex.org/W4415744218","doi":"https://doi.org/10.1109/sbcci66862.2025.11218646"},"language":null,"primary_location":{"id":"doi:10.1109/sbcci66862.2025.11218646","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci66862.2025.11218646","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 38th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012094754","display_name":"Tiago Oliveira Weber","orcid":"https://orcid.org/0000-0003-3993-9341"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Tiago Oliveira Weber","raw_affiliation_strings":["Federal University of Rio Grande do Sul,Porto Alegre,Brazil"],"affiliations":[{"raw_affiliation_string":"Federal University of Rio Grande do Sul,Porto Alegre,Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035158980","display_name":"Fabian L. Cabrera","orcid":"https://orcid.org/0000-0002-8409-2103"},"institutions":[{"id":"https://openalex.org/I4104125","display_name":"Universidade Federal de Santa Catarina","ror":"https://ror.org/041akq887","country_code":"BR","type":"education","lineage":["https://openalex.org/I4104125"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Fabi\u00e1n Leonardo Cabrera","raw_affiliation_strings":["Federal University of Santa Catarina,Florian&#x00F3;polis,Brazil"],"affiliations":[{"raw_affiliation_string":"Federal University of Santa Catarina,Florian&#x00F3;polis,Brazil","institution_ids":["https://openalex.org/I4104125"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5012094754"],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16554354,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.352400004863739,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.352400004863739,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.2143000066280365,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.12460000067949295,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8104000091552734},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.5277000069618225},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.46540001034736633},{"id":"https://openalex.org/keywords/artificial-neuron","display_name":"Artificial neuron","score":0.4388999938964844},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.43140000104904175},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.39730000495910645},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.38440001010894775}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8104000091552734},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6169999837875366},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5277000069618225},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47690001130104065},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.46540001034736633},{"id":"https://openalex.org/C2776990819","wikidata":"https://www.wikidata.org/wiki/Q177058","display_name":"Artificial neuron","level":3,"score":0.4388999938964844},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.43140000104904175},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.39730000495910645},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.38440001010894775},{"id":"https://openalex.org/C204323151","wikidata":"https://www.wikidata.org/wiki/Q905424","display_name":"Range (aeronautics)","level":2,"score":0.3619999885559082},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3490999937057495},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.29649999737739563},{"id":"https://openalex.org/C186565885","wikidata":"https://www.wikidata.org/wiki/Q1651163","display_name":"Biological neuron model","level":3,"score":0.29179999232292175},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.2743000090122223},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26840001344680786},{"id":"https://openalex.org/C115051666","wikidata":"https://www.wikidata.org/wiki/Q6522493","display_name":"Ranging","level":2,"score":0.26809999346733093},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2644999921321869},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2547000050544739}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/sbcci66862.2025.11218646","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci66862.2025.11218646","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 38th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320322025","display_name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","ror":"https://ror.org/03swz6y49"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W2034326903","https://openalex.org/W2044406471","https://openalex.org/W2148253689","https://openalex.org/W2276069931","https://openalex.org/W2725092576","https://openalex.org/W2799818742","https://openalex.org/W2801748224","https://openalex.org/W2978469638","https://openalex.org/W3083292807","https://openalex.org/W3084541914","https://openalex.org/W3106107285","https://openalex.org/W3120016950","https://openalex.org/W3127329944","https://openalex.org/W3196061840","https://openalex.org/W4283689376","https://openalex.org/W4292070784","https://openalex.org/W4409019733"],"related_works":[],"abstract_inverted_index":{"The":[0,61],"use":[1,62],"of":[2,22,63,73,106,114,127],"artificial":[3],"intelligence":[4],"techniques":[5,78],"is":[6],"improving":[7],"solutions":[8],"across":[9],"multiple":[10],"fields.":[11],"To":[12],"accomplish":[13],"that,":[14],"they":[15],"require":[16],"to":[17,32,55,108,121],"perform":[18,33],"a":[19,45,70,87,94,111,132],"great":[20,71],"number":[21],"operations.":[23],"On":[24],"the":[25,99],"hardware":[26],"side,":[27],"neuron":[28,49,97,100],"topologies":[29],"are":[30],"required":[31],"these":[34],"operations":[35],"with":[36,51,69],"reduced":[37,57],"power":[38],"consumption":[39],"and":[40,123],"area.":[41],"This":[42],"work":[43],"presents":[44],"small":[46],"CMOS":[47,65,88],"analog":[48],"topology":[50],"digital":[52],"weights":[53,119],"designed":[54],"achieve":[56],"area":[58,126],"an":[59,103,124],"power.":[60],"standard":[64],"technology":[66],"allows":[67],"integration":[68],"variety":[72],"applications":[74],"without":[75],"requiring":[76],"special":[77],"for":[79,93,131],"combining":[80],"different":[81],"technologies.":[82],"Simulations":[83],"were":[84],"performed":[85],"in":[86],"65":[89],"nm":[90],"technology.":[91],"Results":[92],"3-bit":[95],"weight":[96],"demonstrate":[98],"complete":[101],"functionality,":[102],"input-output":[104],"range":[105],"0.2":[107],"1.0":[109],"V,":[110],"maximum":[112],"current":[113],"$23.45":[115],"\\mu":[116,129],"\\mathrm{~A}$":[117],"(with":[118],"set":[120],"maximum)":[122],"estimated":[125],"$57":[128],"m^{2}$":[130],"two-input":[133],"neuron.":[134]},"counts_by_year":[],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-10-31T00:00:00"}
