{"id":"https://openalex.org/W2900553505","doi":"https://doi.org/10.1109/sbcci.2018.8533251","title":"BANCS: Bidirectional Alternating Nanomagnetic Clocking Scheme","display_name":"BANCS: Bidirectional Alternating Nanomagnetic Clocking Scheme","publication_year":2018,"publication_date":"2018-08-01","ids":{"openalex":"https://openalex.org/W2900553505","doi":"https://doi.org/10.1109/sbcci.2018.8533251","mag":"2900553505"},"language":"en","primary_location":{"id":"doi:10.1109/sbcci.2018.8533251","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci.2018.8533251","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090527890","display_name":"Ruan Evangelista Formigoni","orcid":"https://orcid.org/0000-0002-1574-3240"},"institutions":[{"id":"https://openalex.org/I146165071","display_name":"Universidade Federal de Vi\u00e7osa","ror":"https://ror.org/0409dgb37","country_code":"BR","type":"education","lineage":["https://openalex.org/I146165071"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Ruan Evangelista Formigoni","raw_affiliation_strings":["Science and Technology Institute, Universidade Federal de Vi\u00e7osa"],"affiliations":[{"raw_affiliation_string":"Science and Technology Institute, Universidade Federal de Vi\u00e7osa","institution_ids":["https://openalex.org/I146165071"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023995796","display_name":"Omar P. Vilela Neto","orcid":"https://orcid.org/0000-0003-1769-0629"},"institutions":[{"id":"https://openalex.org/I4210156583","display_name":"Laboratoire d'Informatique de Paris-Nord","ror":"https://ror.org/05g1zjw44","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210091279","https://openalex.org/I4210156583","https://openalex.org/I4210159245"]},{"id":"https://openalex.org/I110200422","display_name":"Universidade Federal de Minas Gerais","ror":"https://ror.org/0176yjw32","country_code":"BR","type":"education","lineage":["https://openalex.org/I110200422"]}],"countries":["BR","FR"],"is_corresponding":false,"raw_author_name":"Omar P. Vilela Neto","raw_affiliation_strings":["Computer Science Department, Universidade Federal de Minas Gerais"],"affiliations":[{"raw_affiliation_string":"Computer Science Department, Universidade Federal de Minas Gerais","institution_ids":["https://openalex.org/I110200422","https://openalex.org/I4210156583"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068177643","display_name":"Jos\u00e9 Augusto M. Nacif","orcid":"https://orcid.org/0000-0003-0703-5620"},"institutions":[{"id":"https://openalex.org/I146165071","display_name":"Universidade Federal de Vi\u00e7osa","ror":"https://ror.org/0409dgb37","country_code":"BR","type":"education","lineage":["https://openalex.org/I146165071"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Jose Augusto M. Nacif","raw_affiliation_strings":["Science and Technology Institute, Universidade Federal de Vi\u00e7osa"],"affiliations":[{"raw_affiliation_string":"Science and Technology Institute, Universidade Federal de Vi\u00e7osa","institution_ids":["https://openalex.org/I146165071"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5090527890"],"corresponding_institution_ids":["https://openalex.org/I146165071"],"apc_list":null,"apc_paid":null,"fwci":1.2116,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.82060871,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6595540046691895},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5942286849021912},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5861406922340393},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5810960531234741},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5546009540557861},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5223297476768494},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5168931484222412},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.4505789279937744},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4297291934490204},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.42542409896850586},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.32502537965774536},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2441195547580719},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1822023093700409},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09643444418907166}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6595540046691895},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5942286849021912},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5861406922340393},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5810960531234741},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5546009540557861},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5223297476768494},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5168931484222412},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.4505789279937744},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4297291934490204},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.42542409896850586},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32502537965774536},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2441195547580719},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1822023093700409},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09643444418907166},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/sbcci.2018.8533251","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci.2018.8533251","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8500000238418579,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1581630807","https://openalex.org/W1987474313","https://openalex.org/W1993788100","https://openalex.org/W2028294129","https://openalex.org/W2033344385","https://openalex.org/W2059030116","https://openalex.org/W2089395964","https://openalex.org/W2107979398","https://openalex.org/W2110711063","https://openalex.org/W2157964406","https://openalex.org/W2169757251","https://openalex.org/W2289736896","https://openalex.org/W2495506608"],"related_works":["https://openalex.org/W2170979950","https://openalex.org/W1980349267","https://openalex.org/W2765435638","https://openalex.org/W2098419840","https://openalex.org/W3010731809","https://openalex.org/W2140610743","https://openalex.org/W2121863912","https://openalex.org/W2152913847","https://openalex.org/W1870848632","https://openalex.org/W2986691431"],"abstract_inverted_index":{"The":[0,14],"CMOS":[1,50],"technology":[2],"is":[3,21,66,152],"reaching":[4],"its":[5],"physical":[6],"limitations":[7],"as":[8],"the":[9,24,54,67,91,104,129,149],"transistors'":[10],"feature":[11],"size":[12],"decreases.":[13],"Nano-magnetic":[15],"Logic":[16],"(NML)":[17],"field-coupled":[18],"nanocomputing":[19],"paradigm":[20],"one":[22],"of":[23,45,56],"promissing":[25],"alternatives":[26],"for":[27,90],"future":[28],"nanotechnologies.":[29],"NML":[30,64,98],"utilizes":[31],"single":[32],"domain":[33],"magnets":[34,76],"to":[35,53,73],"implement":[36],"digital":[37],"logic":[38,93],"with":[39,134],"switching":[40],"energies":[41],"that":[42,143],"are":[43,77],"orders":[44],"magnitude":[46],"lower":[47],"than":[48],"a":[49,86,153],"transistor":[51],"due":[52],"absence":[55],"static":[57],"energy.":[58],"An":[59],"important":[60],"issue":[61],"when":[62,75],"designing":[63],"circuits":[65],"thermal":[68,105],"noise":[69,106],"effect,":[70],"which":[71],"leads":[72],"errors":[74],"consecutively":[78],"switched.":[79],"In":[80],"this":[81],"paper":[82],"we":[83],"propose":[84],"BANCS,":[85],"novel":[87],"clocking":[88,99],"scheme":[89],"nanomagnetic":[92],"technology.":[94],"BANCS":[95,111,145],"standardizes":[96],"three-phase":[97],"system,":[100],"and":[101,121,135],"also":[102],"minimizes":[103],"effect.":[107],"We":[108,127],"have":[109],"validated":[110],"using":[112],"three":[113],"circuits:":[114],"XOR":[115],"gate,":[116],"C17":[117],"ISCAS":[118],"85":[119],"benchmark,":[120],"Tougaw":[122],"4-bit":[123],"ripple":[124],"carry":[125],"adder.":[126],"compare":[128],"area":[130,147],"occupied":[131],"by":[132],"versions":[133],"without":[136],"our":[137],"clock":[138],"scheme.":[139],"Our":[140],"results":[141],"show":[142],"although":[144],"imposes":[146],"overhead,":[148],"scalability":[150],"gain":[151],"good":[154],"tradeoff.":[155]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
