{"id":"https://openalex.org/W2000544799","doi":"https://doi.org/10.1109/sbcci.2013.6644860","title":"A methodology to evaluate the aging impact on flip-flops performance","display_name":"A methodology to evaluate the aging impact on flip-flops performance","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2000544799","doi":"https://doi.org/10.1109/sbcci.2013.6644860","mag":"2000544799"},"language":"en","primary_location":{"id":"doi:10.1109/sbcci.2013.6644860","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci.2013.6644860","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026708395","display_name":"Cicero S. Nunes","orcid":null},"institutions":[{"id":"https://openalex.org/I94328231","display_name":"University of Rio Grande and Rio Grande Community College","ror":"https://ror.org/02sghbs34","country_code":"US","type":"education","lineage":["https://openalex.org/I94328231"]},{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR","US"],"is_corresponding":true,"raw_author_name":"Cicero Nunes","raw_affiliation_strings":["Institute of Informatics, Federal University of Rio Grande do Sul, Porto Alegre, Brazil","Inst. of Inf., Fed. Univ. of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Institute of Informatics, Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Inst. of Inf., Fed. Univ. of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723","https://openalex.org/I94328231"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062131940","display_name":"Paulo F. Butzen","orcid":"https://orcid.org/0000-0003-1587-7596"},"institutions":[{"id":"https://openalex.org/I126460647","display_name":"Universidade Federal do Rio Grande","ror":"https://ror.org/05hpfkn88","country_code":"BR","type":"education","lineage":["https://openalex.org/I126460647"]},{"id":"https://openalex.org/I94328231","display_name":"University of Rio Grande and Rio Grande Community College","ror":"https://ror.org/02sghbs34","country_code":"US","type":"education","lineage":["https://openalex.org/I94328231"]}],"countries":["BR","US"],"is_corresponding":false,"raw_author_name":"Paulo F. Butzen","raw_affiliation_strings":["Center for Computational Science, Federal University of Rio Grande, Brazil","Center for Comput. Sci., Fed. Univ. of Rio Grande-FURG, Rio Grande, Brazil"],"affiliations":[{"raw_affiliation_string":"Center for Computational Science, Federal University of Rio Grande, Brazil","institution_ids":["https://openalex.org/I126460647"]},{"raw_affiliation_string":"Center for Comput. Sci., Fed. Univ. of Rio Grande-FURG, Rio Grande, Brazil","institution_ids":["https://openalex.org/I94328231","https://openalex.org/I126460647"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065397615","display_name":"Andr\u00e9 I. Reis","orcid":"https://orcid.org/0000-0002-3118-8160"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]},{"id":"https://openalex.org/I94328231","display_name":"University of Rio Grande and Rio Grande Community College","ror":"https://ror.org/02sghbs34","country_code":"US","type":"education","lineage":["https://openalex.org/I94328231"]}],"countries":["BR","US"],"is_corresponding":false,"raw_author_name":"Andre I. Reis","raw_affiliation_strings":["Institute of Informatics, Federal University of Rio Grande do Sul, Porto Alegre, Brazil","Inst. of Inf., Fed. Univ. of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Institute of Informatics, Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Inst. of Inf., Fed. Univ. of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723","https://openalex.org/I94328231"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]},{"id":"https://openalex.org/I94328231","display_name":"University of Rio Grande and Rio Grande Community College","ror":"https://ror.org/02sghbs34","country_code":"US","type":"education","lineage":["https://openalex.org/I94328231"]}],"countries":["BR","US"],"is_corresponding":false,"raw_author_name":"Renato P. Ribas","raw_affiliation_strings":["Institute of Informatics, Federal University of Rio Grande do Sul, Porto Alegre, Brazil","Inst. of Inf., Fed. Univ. of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Institute of Informatics, Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Inst. of Inf., Fed. Univ. of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723","https://openalex.org/I94328231"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5026708395"],"corresponding_institution_ids":["https://openalex.org/I130442723","https://openalex.org/I94328231"],"apc_list":null,"apc_paid":null,"fwci":0.2364,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.58694669,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"32","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.6970177292823792},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6351152658462524},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.6218695044517517},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5967000722885132},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5961344242095947},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5768355131149292},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5563381314277649},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5525286197662354},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4875340163707733},{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.4714340269565582},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4530656933784485},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3968397080898285},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3455953598022461},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3180620074272156},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.25595909357070923},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2312384843826294},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16797193884849548}],"concepts":[{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.6970177292823792},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6351152658462524},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.6218695044517517},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5967000722885132},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5961344242095947},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5768355131149292},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5563381314277649},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5525286197662354},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4875340163707733},{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.4714340269565582},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4530656933784485},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3968397080898285},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3455953598022461},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3180620074272156},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25595909357070923},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2312384843826294},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16797193884849548},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/sbcci.2013.6644860","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci.2013.6644860","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321091","display_name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","ror":"https://ror.org/00x0ma614"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1594033353","https://openalex.org/W1982273278","https://openalex.org/W1991025821","https://openalex.org/W1996078258","https://openalex.org/W2048459293","https://openalex.org/W2069345435","https://openalex.org/W2076372184","https://openalex.org/W2081332285","https://openalex.org/W2103792078","https://openalex.org/W2107944009","https://openalex.org/W2109195618","https://openalex.org/W2112096506","https://openalex.org/W2113458531","https://openalex.org/W2113735631","https://openalex.org/W2124460294","https://openalex.org/W2127614267","https://openalex.org/W2139250338","https://openalex.org/W2139286506","https://openalex.org/W2144085963","https://openalex.org/W2151092072","https://openalex.org/W2153772101","https://openalex.org/W2158245653","https://openalex.org/W2170333286","https://openalex.org/W3089937351","https://openalex.org/W6662848530","https://openalex.org/W6676401042","https://openalex.org/W6677134411","https://openalex.org/W6678264165"],"related_works":["https://openalex.org/W2262031297","https://openalex.org/W2733322820","https://openalex.org/W2482318635","https://openalex.org/W2020161494","https://openalex.org/W2045056374","https://openalex.org/W2298981088","https://openalex.org/W818963952","https://openalex.org/W1939541994","https://openalex.org/W1851795671","https://openalex.org/W2146663621"],"abstract_inverted_index":{"The":[0,39],"impact":[1],"of":[2,7,14],"aging":[3,35],"effects,":[4],"in":[5,19,37],"terms":[6],"circuit":[8],"performance":[9],"and":[10,50,71],"reliability,":[11],"is":[12,48],"one":[13],"the":[15,23,73],"new":[16],"recent":[17],"challenges":[18],"VLSI":[20],"design":[21],"targeting":[22],"most":[24],"advanced":[25],"CMOS":[26],"technologies.":[27],"This":[28],"work":[29],"proposes":[30],"an":[31],"effective":[32],"methodology":[33],"to":[34,53,69],"analysis":[36],"flip-flops.":[38],"estimation":[40],"method":[41],"proposed":[42,74],"previously":[43],"for":[44],"combinational":[45],"logic":[46],"gates":[47],"exploited":[49],"improved":[51],"herein":[52],"address":[54],"such":[55],"sequential":[56],"gates.":[57],"Three":[58],"different":[59],"conventional":[60],"static":[61],"flip-flops":[62],"have":[63],"been":[64],"used":[65],"as":[66],"case":[67],"studies":[68],"demonstrate":[70],"validate":[72],"methodology.":[75]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}