{"id":"https://openalex.org/W1976597925","doi":"https://doi.org/10.1109/sbcci.2013.6644854","title":"Improving the methodology to build non-series-parallel transistor arrangements","display_name":"Improving the methodology to build non-series-parallel transistor arrangements","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W1976597925","doi":"https://doi.org/10.1109/sbcci.2013.6644854","mag":"1976597925"},"language":"en","primary_location":{"id":"doi:10.1109/sbcci.2013.6644854","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci.2013.6644854","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031641596","display_name":"Vinicius N. Possani","orcid":"https://orcid.org/0000-0003-4334-1174"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Vinicius N. Possani","raw_affiliation_strings":["Group of Architectures and Integrated Circuits, Federal University of Pelotas - UFPel, Pelotas, Brazil","Group of Archit. & Integrated Circuits, Fed. Univ. of Pelotas - UFPel, Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits, Federal University of Pelotas - UFPel, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Group of Archit. & Integrated Circuits, Fed. Univ. of Pelotas - UFPel, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5105354099","display_name":"Vinicius Callegaro","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]},{"id":"https://openalex.org/I94328231","display_name":"University of Rio Grande and Rio Grande Community College","ror":"https://ror.org/02sghbs34","country_code":"US","type":"education","lineage":["https://openalex.org/I94328231"]}],"countries":["BR","US"],"is_corresponding":false,"raw_author_name":"Vinicius Callegaro","raw_affiliation_strings":["Institute of Informatics, Federal University of Rio Grande do Sul \u2013 UFRGS, Porto Alegre, Brazil","Inst. of Inf., Fed. Univ. of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Institute of Informatics, Federal University of Rio Grande do Sul \u2013 UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Inst. of Inf., Fed. Univ. of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723","https://openalex.org/I94328231"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065397615","display_name":"Andr\u00e9 I. Reis","orcid":"https://orcid.org/0000-0002-3118-8160"},"institutions":[{"id":"https://openalex.org/I94328231","display_name":"University of Rio Grande and Rio Grande Community College","ror":"https://ror.org/02sghbs34","country_code":"US","type":"education","lineage":["https://openalex.org/I94328231"]},{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR","US"],"is_corresponding":false,"raw_author_name":"Andre I. Reis","raw_affiliation_strings":["Institute of Informatics, Federal University of Rio Grande do Sul \u2013 UFRGS, Porto Alegre, Brazil","Inst. of Inf., Fed. Univ. of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Institute of Informatics, Federal University of Rio Grande do Sul \u2013 UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Inst. of Inf., Fed. Univ. of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723","https://openalex.org/I94328231"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]},{"id":"https://openalex.org/I94328231","display_name":"University of Rio Grande and Rio Grande Community College","ror":"https://ror.org/02sghbs34","country_code":"US","type":"education","lineage":["https://openalex.org/I94328231"]}],"countries":["BR","US"],"is_corresponding":false,"raw_author_name":"Renato P. Ribas","raw_affiliation_strings":["Institute of Informatics, Federal University of Rio Grande do Sul \u2013 UFRGS, Porto Alegre, Brazil","Inst. of Inf., Fed. Univ. of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Institute of Informatics, Federal University of Rio Grande do Sul \u2013 UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Inst. of Inf., Fed. Univ. of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723","https://openalex.org/I94328231"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068796829","display_name":"Felipe Marques","orcid":"https://orcid.org/0000-0003-1318-9992"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Felipe S. Marques","raw_affiliation_strings":["Group of Architectures and Integrated Circuits, Federal University of Pelotas - UFPel, Pelotas, Brazil","Group of Archit. & Integrated Circuits, Fed. Univ. of Pelotas - UFPel, Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits, Federal University of Pelotas - UFPel, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Group of Archit. & Integrated Circuits, Fed. Univ. of Pelotas - UFPel, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014303947","display_name":"Leomar S. da Rosa","orcid":"https://orcid.org/0000-0002-7150-5685"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Leomar S. da Rosa","raw_affiliation_strings":["Group of Architectures and Integrated Circuits, Federal University of Pelotas - UFPel, Pelotas, Brazil","Group of Archit. & Integrated Circuits, Fed. Univ. of Pelotas - UFPel, Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits, Federal University of Pelotas - UFPel, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Group of Archit. & Integrated Circuits, Fed. Univ. of Pelotas - UFPel, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5031641596"],"corresponding_institution_ids":["https://openalex.org/I169248161"],"apc_list":null,"apc_paid":null,"fwci":0.4729,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.67170415,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7203794121742249},{"id":"https://openalex.org/keywords/series","display_name":"Series (stratigraphy)","score":0.640981137752533},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.56419837474823},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5334753394126892},{"id":"https://openalex.org/keywords/series-and-parallel-circuits","display_name":"Series and parallel circuits","score":0.5290837287902832},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4674568772315979},{"id":"https://openalex.org/keywords/greedy-algorithm","display_name":"Greedy algorithm","score":0.46290716528892517},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4501023292541504},{"id":"https://openalex.org/keywords/property","display_name":"Property (philosophy)","score":0.4473504424095154},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.29913896322250366},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.29026657342910767},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1169787049293518},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09068062901496887},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07115671038627625}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7203794121742249},{"id":"https://openalex.org/C143724316","wikidata":"https://www.wikidata.org/wiki/Q312468","display_name":"Series (stratigraphy)","level":2,"score":0.640981137752533},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.56419837474823},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5334753394126892},{"id":"https://openalex.org/C95023266","wikidata":"https://www.wikidata.org/wiki/Q55738334","display_name":"Series and parallel circuits","level":3,"score":0.5290837287902832},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4674568772315979},{"id":"https://openalex.org/C51823790","wikidata":"https://www.wikidata.org/wiki/Q504353","display_name":"Greedy algorithm","level":2,"score":0.46290716528892517},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4501023292541504},{"id":"https://openalex.org/C189950617","wikidata":"https://www.wikidata.org/wiki/Q937228","display_name":"Property (philosophy)","level":2,"score":0.4473504424095154},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.29913896322250366},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.29026657342910767},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1169787049293518},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09068062901496887},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07115671038627625},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/sbcci.2013.6644854","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci.2013.6644854","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321091","display_name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","ror":"https://ror.org/00x0ma614"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1511688816","https://openalex.org/W1546585099","https://openalex.org/W1963548198","https://openalex.org/W1994996301","https://openalex.org/W2015987974","https://openalex.org/W2031298013","https://openalex.org/W2033704098","https://openalex.org/W2040537281","https://openalex.org/W2078179095","https://openalex.org/W2087907893","https://openalex.org/W2105789204","https://openalex.org/W2141516637","https://openalex.org/W2159683499","https://openalex.org/W2170230760"],"related_works":["https://openalex.org/W4387497383","https://openalex.org/W3183948672","https://openalex.org/W3173606202","https://openalex.org/W3110381201","https://openalex.org/W2948807893","https://openalex.org/W2935909890","https://openalex.org/W2778153218","https://openalex.org/W2758277628","https://openalex.org/W1531601525","https://openalex.org/W43018993"],"abstract_inverted_index":{"This":[0,53],"paper":[1],"presents":[2],"an":[3,58],"improvement":[4],"in":[5],"our":[6,37],"previous":[7],"methodology":[8,38,82],"to":[9,23,42,57,65,85],"generate":[10],"efficient":[11],"transistor":[12,31],"networks.":[13],"The":[14,33],"proposed":[15],"method":[16],"applies":[17],"graph-based":[18],"optimizations":[19],"and":[20,26],"is":[21,39,55],"capable":[22],"deliver":[24],"series-parallel":[25],"non-series-parallel":[27],"arrangements":[28],"with":[29],"reduced":[30],"count.":[32],"main":[34],"feature":[35],"of":[36,49,70,80],"the":[40,47,50,67,71,78],"possibility":[41],"avoid":[43],"greedy":[44,72],"choices":[45],"during":[46],"beginning":[48],"optimization":[51],"process.":[52],"property":[54],"associated":[56],"edges":[59],"compression":[60],"technique":[61],"that":[62],"also":[63],"contributes":[64],"minimize":[66],"bad":[68],"effect":[69],"choices.":[73],"Performed":[74],"experiments":[75],"have":[76],"demonstrated":[77],"efficiency":[79],"this":[81],"when":[83],"comparing":[84],"other":[86],"available":[87],"techniques.":[88]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
