{"id":"https://openalex.org/W1990329597","doi":"https://doi.org/10.1109/sbcci.2013.6644850","title":"An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs","display_name":"An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W1990329597","doi":"https://doi.org/10.1109/sbcci.2013.6644850","mag":"1990329597"},"language":"en","primary_location":{"id":"doi:10.1109/sbcci.2013.6644850","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci.2013.6644850","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051947757","display_name":"Johanna Sep\u00falveda","orcid":"https://orcid.org/0000-0001-9550-1219"},"institutions":[{"id":"https://openalex.org/I17974374","display_name":"Universidade de S\u00e3o Paulo","ror":"https://ror.org/036rp1748","country_code":"BR","type":"education","lineage":["https://openalex.org/I17974374"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Johanna Sepulveda","raw_affiliation_strings":["Universidade de Sao Paulo, Sao Paulo, S\u00c3\u00a3o Paulo, BR","Microelectron. Lab. LME, Univ. of Sao Paulo, Sao Paulo, Brazil"],"affiliations":[{"raw_affiliation_string":"Universidade de Sao Paulo, Sao Paulo, S\u00c3\u00a3o Paulo, BR","institution_ids":["https://openalex.org/I17974374"]},{"raw_affiliation_string":"Microelectron. Lab. LME, Univ. of Sao Paulo, Sao Paulo, Brazil","institution_ids":["https://openalex.org/I17974374"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015669050","display_name":"Guy Gogniat","orcid":"https://orcid.org/0000-0002-9528-5277"},"institutions":[{"id":"https://openalex.org/I2802204017","display_name":"Universit\u00e9 de Bretagne Sud","ror":"https://ror.org/04ed7fw48","country_code":"FR","type":"education","lineage":["https://openalex.org/I2802204017"]},{"id":"https://openalex.org/I161929037","display_name":"Universit\u00e9 de Bretagne Occidentale","ror":"https://ror.org/01b8h3982","country_code":"FR","type":"education","lineage":["https://openalex.org/I161929037"]},{"id":"https://openalex.org/I4210123702","display_name":"Laboratoire des Sciences et Techniques de l\u2019Information de la Communication et de la Connaissance","ror":"https://ror.org/0266kfd37","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I180375564","https://openalex.org/I201181511","https://openalex.org/I205703379","https://openalex.org/I2802204017","https://openalex.org/I4210123702","https://openalex.org/I4210127572","https://openalex.org/I4210145102","https://openalex.org/I4210145102","https://openalex.org/I4210159245","https://openalex.org/I4412460332"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Guy Gogniat","raw_affiliation_strings":["Information and Communication Science and Technology Laboratory Lab-STICC, Universit\u00e9 Bretagne Sud, France","Inf. & Commun. Sci. & Technol. Lab., Univ. Bretagne Sud, Lorient, France"],"affiliations":[{"raw_affiliation_string":"Information and Communication Science and Technology Laboratory Lab-STICC, Universit\u00e9 Bretagne Sud, France","institution_ids":["https://openalex.org/I2802204017","https://openalex.org/I161929037","https://openalex.org/I4210123702"]},{"raw_affiliation_string":"Inf. & Commun. Sci. & Technol. Lab., Univ. Bretagne Sud, Lorient, France","institution_ids":["https://openalex.org/I2802204017"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044117098","display_name":"Ricardo Pires","orcid":"https://orcid.org/0000-0003-4677-8435"},"institutions":[{"id":"https://openalex.org/I17974374","display_name":"Universidade de S\u00e3o Paulo","ror":"https://ror.org/036rp1748","country_code":"BR","type":"education","lineage":["https://openalex.org/I17974374"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Ricardo Pires","raw_affiliation_strings":["Microelectronics Laboratory LME, University of S\u00e3o Paulo, Brazil","Microelectron. Lab. LME, Univ. of Sao Paulo, Sao Paulo, Brazil"],"affiliations":[{"raw_affiliation_string":"Microelectronics Laboratory LME, University of S\u00e3o Paulo, Brazil","institution_ids":["https://openalex.org/I17974374"]},{"raw_affiliation_string":"Microelectron. Lab. LME, Univ. of Sao Paulo, Sao Paulo, Brazil","institution_ids":["https://openalex.org/I17974374"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045814236","display_name":"Wang Jiang Chau","orcid":"https://orcid.org/0000-0002-3960-4026"},"institutions":[{"id":"https://openalex.org/I17974374","display_name":"Universidade de S\u00e3o Paulo","ror":"https://ror.org/036rp1748","country_code":"BR","type":"education","lineage":["https://openalex.org/I17974374"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Wang Chau","raw_affiliation_strings":["Microelectronics Laboratory LME, University of S\u00e3o Paulo, Brazil","Microelectron. Lab. LME, Univ. of Sao Paulo, Sao Paulo, Brazil"],"affiliations":[{"raw_affiliation_string":"Microelectronics Laboratory LME, University of S\u00e3o Paulo, Brazil","institution_ids":["https://openalex.org/I17974374"]},{"raw_affiliation_string":"Microelectron. Lab. LME, Univ. of Sao Paulo, Sao Paulo, Brazil","institution_ids":["https://openalex.org/I17974374"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5106446871","display_name":"Marius Strum","orcid":null},"institutions":[{"id":"https://openalex.org/I17974374","display_name":"Universidade de S\u00e3o Paulo","ror":"https://ror.org/036rp1748","country_code":"BR","type":"education","lineage":["https://openalex.org/I17974374"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Marius Strum","raw_affiliation_strings":["Microelectronics Laboratory LME, University of S\u00e3o Paulo, Brazil","Microelectron. Lab. LME, Univ. of Sao Paulo, Sao Paulo, Brazil"],"affiliations":[{"raw_affiliation_string":"Microelectronics Laboratory LME, University of S\u00e3o Paulo, Brazil","institution_ids":["https://openalex.org/I17974374"]},{"raw_affiliation_string":"Microelectron. Lab. LME, Univ. of Sao Paulo, Sao Paulo, Brazil","institution_ids":["https://openalex.org/I17974374"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5051947757"],"corresponding_institution_ids":["https://openalex.org/I17974374"],"apc_list":null,"apc_paid":null,"fwci":0.3625,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.6327711,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"4","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9943000078201294,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.983299970626831,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.9159109592437744},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7333087921142578},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6066012978553772},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5920634865760803},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5807417035102844},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.5686174631118774},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5156525373458862},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5032688975334167},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4554029703140259},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.4523162245750427},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.40676233172416687},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3394937515258789},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.3358767330646515},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2799578905105591},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.135980486869812},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10472646355628967}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.9159109592437744},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7333087921142578},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6066012978553772},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5920634865760803},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5807417035102844},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.5686174631118774},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5156525373458862},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5032688975334167},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4554029703140259},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.4523162245750427},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.40676233172416687},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3394937515258789},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.3358767330646515},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2799578905105591},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.135980486869812},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10472646355628967},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/sbcci.2013.6644850","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci.2013.6644850","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8600000143051147}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W191514637","https://openalex.org/W1539772332","https://openalex.org/W1997589541","https://openalex.org/W2011039300","https://openalex.org/W2150206286","https://openalex.org/W2152530926","https://openalex.org/W4205615784","https://openalex.org/W4206989268","https://openalex.org/W4285719527","https://openalex.org/W4292544546","https://openalex.org/W6649778161","https://openalex.org/W6682247895"],"related_works":["https://openalex.org/W4230458348","https://openalex.org/W3198758847","https://openalex.org/W4297990507","https://openalex.org/W2144563801","https://openalex.org/W2540211551","https://openalex.org/W2544224778","https://openalex.org/W4247396403","https://openalex.org/W1966854952","https://openalex.org/W2020034302","https://openalex.org/W1990329597"],"abstract_inverted_index":{"Three":[0,35],"dimensional":[1,36],"Multiprocessor":[2],"System-on-Chip":[3],"(3D-MPSoC)":[4],"adoption.":[5],"It":[6],"is":[7,26,39],"characterized":[8],"by":[9,149],"the":[10,29,33,42,56,69,76,84,93,130,144,150],"integration":[11],"of":[12,16,28,32,45,75,83],"a":[13,20,60,123],"large":[14],"amount":[15],"hardware":[17],"components":[18],"on":[19,109,158],"single":[21,106,113],"multilayer":[22],"chip.":[23],"However,":[24],"heating":[25,73,151],"one":[27],"major":[30],"pitfalls":[31],"3D-MPSoCs.":[34,46],"Network-on-Chip":[37],"(3D-NoC)":[38],"used":[40],"as":[41,143],"communication":[43],"structure":[44],"Its":[47],"main":[48],"role":[49],"in":[50,88],"system":[51],"operation":[52],"and":[53,72,79,96,100,114,134,138,171],"performance":[54,95],"makes":[55],"optimal":[57],"3D-NoC":[58,64,89,98,132,164],"design":[59],"critical":[61,86],"task.":[62],"Final":[63],"configuration":[65],"must":[66],"fulfill":[67],"all":[68],"application":[70,107],"requirements":[71],"constraints":[74],"system.":[77],"Topology":[78],"mapping":[80,101,135],"are":[81,141],"some":[82],"most":[85],"parameters":[87],"design,":[90],"strongly":[91],"influencing":[92],"3D-MPSoC":[94,160],"cost.":[97],"topology":[99,133],"has":[102,155],"been":[103,156],"solved":[104],"for":[105],"systems":[108],"homogeneous":[110],"3D-NoCs":[111],"using":[112],"multi-objective":[115,124,146],"optimization":[116],"algorithms.":[117],"In":[118],"this":[119],"paper":[120],"we":[121],"use":[122],"immune":[125],"algorithm":[126],"(MIA),":[127],"to":[128,168,177],"solve":[129],"multi-application":[131],"problems.":[136],"Latency":[137],"power":[139,170],"consumption":[140],"adopted":[142],"target":[145],"functions":[147],"constrained":[148],"function.":[152],"Our":[153],"strategy":[154],"applied":[157],"8":[159],"benchmarks.":[161],"Their":[162],"final":[163],"configurations":[165],"have":[166],"up":[167],"73%":[169],"42%":[172],"latency":[173],"enhancement":[174],"when":[175],"compared":[176],"previous":[178],"reported":[179],"results.":[180]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}