{"id":"https://openalex.org/W4245667823","doi":"https://doi.org/10.1109/sbcci.2003.1232830","title":"Modeling a reconfigurable system for computing the FFT in place via rewriting-logic","display_name":"Modeling a reconfigurable system for computing the FFT in place via rewriting-logic","publication_year":2004,"publication_date":"2004-01-23","ids":{"openalex":"https://openalex.org/W4245667823","doi":"https://doi.org/10.1109/sbcci.2003.1232830"},"language":"en","primary_location":{"id":"doi:10.1109/sbcci.2003.1232830","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci.2003.1232830","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043206848","display_name":"Maur\u00edcio Ayala-Rinc\u00f3n","orcid":"https://orcid.org/0000-0003-0089-3905"},"institutions":[{"id":"https://openalex.org/I150729083","display_name":"Universidade de Bras\u00edlia","ror":"https://ror.org/02xfp8v59","country_code":"BR","type":"education","lineage":["https://openalex.org/I150729083"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"M. Ayala-Rincon","raw_affiliation_strings":["Departamentos de Matem\u00e1tica, Universidade de Bras\u00edlia, Brazil"],"affiliations":[{"raw_affiliation_string":"Departamentos de Matem\u00e1tica, Universidade de Bras\u00edlia, Brazil","institution_ids":["https://openalex.org/I150729083"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104060267","display_name":"R.B. Nogueira","orcid":null},"institutions":[{"id":"https://openalex.org/I150729083","display_name":"Universidade de Bras\u00edlia","ror":"https://ror.org/02xfp8v59","country_code":"BR","type":"education","lineage":["https://openalex.org/I150729083"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"R.B. Nogueira","raw_affiliation_strings":["Engenharia Mec\u00e2nica, Universidade de Bras\u00edlia, Brazil"],"affiliations":[{"raw_affiliation_string":"Engenharia Mec\u00e2nica, Universidade de Bras\u00edlia, Brazil","institution_ids":["https://openalex.org/I150729083"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042189424","display_name":"Carlos H. Llanos","orcid":"https://orcid.org/0000-0002-0115-4461"},"institutions":[{"id":"https://openalex.org/I150729083","display_name":"Universidade de Bras\u00edlia","ror":"https://ror.org/02xfp8v59","country_code":"BR","type":"education","lineage":["https://openalex.org/I150729083"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"C.H. Llanos","raw_affiliation_strings":["Engenharia Mec\u00e2nica, Universidade de Bras\u00edlia, Brazil"],"affiliations":[{"raw_affiliation_string":"Engenharia Mec\u00e2nica, Universidade de Bras\u00edlia, Brazil","institution_ids":["https://openalex.org/I150729083"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019378528","display_name":"Ricardo Pezzuol Jacobi","orcid":"https://orcid.org/0000-0002-4520-7641"},"institutions":[{"id":"https://openalex.org/I150729083","display_name":"Universidade de Bras\u00edlia","ror":"https://ror.org/02xfp8v59","country_code":"BR","type":"education","lineage":["https://openalex.org/I150729083"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"R.P. Jacobi","raw_affiliation_strings":["Ci\u00eancia da Computa\u00e7\u00e3o, Universidade de Bras\u00edlia, Brazil"],"affiliations":[{"raw_affiliation_string":"Ci\u00eancia da Computa\u00e7\u00e3o, Universidade de Bras\u00edlia, Brazil","institution_ids":["https://openalex.org/I150729083"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037848636","display_name":"Reiner W. Hartenstein","orcid":null},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"R.W. Hartenstein","raw_affiliation_strings":["Fachbereich Informatik, Universit\u00e4t Kaiserslautern, Germany"],"affiliations":[{"raw_affiliation_string":"Fachbereich Informatik, Universit\u00e4t Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5043206848"],"corresponding_institution_ids":["https://openalex.org/I150729083"],"apc_list":null,"apc_paid":null,"fwci":1.0532,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.78520162,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1346","issue":null,"first_page":"205","last_page":"210"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/rewriting","display_name":"Rewriting","score":0.863316535949707},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8216334581375122},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7751786112785339},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.6494871973991394},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6079123020172119},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5752590298652649},{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.5482367873191833},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.5186187624931335},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4789717197418213},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4547644257545471},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4325382709503174},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3620656132698059},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3473016619682312},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.339984655380249},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3158419132232666},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1436161994934082},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07567635178565979}],"concepts":[{"id":"https://openalex.org/C154690210","wikidata":"https://www.wikidata.org/wiki/Q1668499","display_name":"Rewriting","level":2,"score":0.863316535949707},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8216334581375122},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7751786112785339},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.6494871973991394},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6079123020172119},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5752590298652649},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.5482367873191833},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.5186187624931335},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4789717197418213},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4547644257545471},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4325382709503174},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3620656132698059},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3473016619682312},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.339984655380249},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3158419132232666},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1436161994934082},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07567635178565979},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/sbcci.2003.1232830","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci.2003.1232830","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W32166614","https://openalex.org/W1487854339","https://openalex.org/W1683919907","https://openalex.org/W1917425894","https://openalex.org/W1973456473","https://openalex.org/W2017711068","https://openalex.org/W2066689215","https://openalex.org/W2091905929","https://openalex.org/W2094969361","https://openalex.org/W2107705503","https://openalex.org/W2147892488","https://openalex.org/W2766554559","https://openalex.org/W4230919050","https://openalex.org/W4372046852","https://openalex.org/W6628929985","https://openalex.org/W6637127530","https://openalex.org/W6639933461"],"related_works":["https://openalex.org/W2204754129","https://openalex.org/W4322751528","https://openalex.org/W2759209791","https://openalex.org/W2340647897","https://openalex.org/W2034458695","https://openalex.org/W1569711686","https://openalex.org/W1541284233","https://openalex.org/W2129154773","https://openalex.org/W2808484818","https://openalex.org/W1991847360"],"abstract_inverted_index":{"The":[0],"growing":[1],"adoption":[2],"of":[3,18,24,42,58,64,92],"reconfigurable":[4,20,61,94],"architectures":[5],"opens":[6],"new":[7,12],"implementation":[8,63],"alternatives":[9,44],"and":[10,28,56],"creates":[11],"design":[13,43,85],"challenges.":[14],"In":[15],"the":[16,22,54,65],"case":[17],"dynamically":[19,60],"architectures,":[21],"choice":[23],"an":[25],"efficient":[26],"architecture":[27],"reconfiguration":[29],"scheme":[30],"for":[31,40,83],"a":[32,36,59,81,89],"given":[33],"application":[34],"is":[35,73],"complex":[37],"task.":[38],"Tools":[39],"exploration":[41],"at":[45],"higher":[46],"abstraction":[47],"levels":[48],"are":[49],"needed.":[50],"This":[51],"paper":[52],"describes":[53],"modeling":[55],"simulation":[57],"hardware":[62],"fast":[66,84],"Fourier":[67],"transform":[68],"(FFT)":[69],"using":[70],"rewriting-logic.":[71],"It":[72],"shown":[74],"that":[75],"rewriting-logic":[76],"can":[77],"be":[78],"used":[79],"as":[80],"framework":[82],"space":[86],"exploration,":[87],"providing":[88],"quick":[90],"evaluation":[91],"different":[93],"solutions.":[95]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
