{"id":"https://openalex.org/W1580033321","doi":"https://doi.org/10.1109/sbcci.2003.1232829","title":"Unified theory to build cell-level transistor networks from BDDs [logic synthesis]","display_name":"Unified theory to build cell-level transistor networks from BDDs [logic synthesis]","publication_year":2004,"publication_date":"2004-01-23","ids":{"openalex":"https://openalex.org/W1580033321","doi":"https://doi.org/10.1109/sbcci.2003.1232829","mag":"1580033321"},"language":"en","primary_location":{"id":"doi:10.1109/sbcci.2003.1232829","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci.2003.1232829","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010469703","display_name":"Renato E. B. Poli","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"R.E.B. Poli","raw_affiliation_strings":["Instituto de Inform\u00e1tica, UFRGS Universidade Federal do Rio Grande do Sul, Porto Alegre, Rio Grande do Sul, Brazil","Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Inform\u00e1tica, UFRGS Universidade Federal do Rio Grande do Sul, Porto Alegre, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067885070","display_name":"Felipe Ribeiro Schneider","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"F.R. Schneider","raw_affiliation_strings":["Instituto de Inform\u00e1tica, UFRGS Universidade Federal do Rio Grande do Sul, Porto Alegre, Rio Grande do Sul, Brazil","Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Inform\u00e1tica, UFRGS Universidade Federal do Rio Grande do Sul, Porto Alegre, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"R.P. Ribas","raw_affiliation_strings":["Instituto de Inform\u00e1tica, UFRGS Universidade Federal do Rio Grande do Sul, Porto Alegre, Rio Grande do Sul, Brazil","Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Inform\u00e1tica, UFRGS Universidade Federal do Rio Grande do Sul, Porto Alegre, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065397615","display_name":"Andr\u00e9 I. Reis","orcid":"https://orcid.org/0000-0002-3118-8160"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"A.I. Reis","raw_affiliation_strings":["Instituto de Inform\u00e1tica, UFRGS Universidade Federal do Rio Grande do Sul, Porto Alegre, Rio Grande do Sul, Brazil","Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Inform\u00e1tica, UFRGS Universidade Federal do Rio Grande do Sul, Porto Alegre, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"9","issue":null,"first_page":"199","last_page":"204"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.7098416090011597},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6435121893882751},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.6126328706741333},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6122915148735046},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5998040437698364},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5584626793861389},{"id":"https://openalex.org/keywords/transistor-count","display_name":"Transistor count","score":0.5209406614303589},{"id":"https://openalex.org/keywords/binary-decision-diagram","display_name":"Binary decision diagram","score":0.4402264952659607},{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.4396599531173706},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4275754988193512},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.42126721143722534},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3973221182823181},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3918074369430542},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.31800758838653564},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2526009678840637},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.20360946655273438},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1994045078754425},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17046794295310974}],"concepts":[{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.7098416090011597},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6435121893882751},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.6126328706741333},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6122915148735046},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5998040437698364},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5584626793861389},{"id":"https://openalex.org/C196320899","wikidata":"https://www.wikidata.org/wiki/Q2623746","display_name":"Transistor count","level":4,"score":0.5209406614303589},{"id":"https://openalex.org/C3309909","wikidata":"https://www.wikidata.org/wiki/Q864155","display_name":"Binary decision diagram","level":2,"score":0.4402264952659607},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.4396599531173706},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4275754988193512},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.42126721143722534},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3973221182823181},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3918074369430542},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.31800758838653564},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2526009678840637},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.20360946655273438},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1994045078754425},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17046794295310974},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/sbcci.2003.1232829","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci.2003.1232829","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320322025","display_name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","ror":"https://ror.org/03swz6y49"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W300217068","https://openalex.org/W1511688816","https://openalex.org/W1738355368","https://openalex.org/W2018094844","https://openalex.org/W2030029202","https://openalex.org/W2080267935","https://openalex.org/W2087118030","https://openalex.org/W2092625136","https://openalex.org/W2143954882","https://openalex.org/W2156028445","https://openalex.org/W2168271575","https://openalex.org/W3150081868","https://openalex.org/W4238983509","https://openalex.org/W6630623413","https://openalex.org/W6684634068"],"related_works":["https://openalex.org/W2299523701","https://openalex.org/W2022195221","https://openalex.org/W2587139111","https://openalex.org/W1999264732","https://openalex.org/W4226211266","https://openalex.org/W2127298806","https://openalex.org/W4295177619","https://openalex.org/W3165307257","https://openalex.org/W2395101366","https://openalex.org/W2734929653"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,39,41,58],"unified":[4],"theory":[5],"to":[6,19,27],"build":[7],"transistor":[8,21,24,43,73,83],"networks":[9,22,84],"through":[10],"binary":[11],"decision":[12],"diagrams":[13],"-":[14],"BDDs.":[15],"It":[16],"is":[17,46,62,75],"able":[18],"obtain":[20],"with":[23],"count":[25],"near":[26],"the":[28,36,65,80],"best":[29],"case":[30],"of":[31,67,82],"other":[32],"methods":[33],"presented":[34],"in":[35],"literature.":[37],"As":[38],"result,":[40],"pass":[42,72],"network":[44],"implementation":[45],"automatically":[47],"generated":[48],"for":[49,64],"XOR-like":[50],"gates,":[51,69],"since":[52],"static":[53,59],"CMOS":[54,60],"performs":[55],"badly.":[56],"Similarly,":[57],"topology":[61],"preferred":[63],"generation":[66],"NAND-like":[68],"on":[70,79],"which":[71],"logic":[74],"not":[76],"optimal.":[77],"Variations":[78],"derivation":[81],"from":[85],"BDDs":[86],"are":[87],"extensively":[88],"discussed.":[89]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
