{"id":"https://openalex.org/W1597839615","doi":"https://doi.org/10.1109/sbcci.2003.1232811","title":"DALI: a methodology for the co-design of dataflow applications on hardware/software architectures [video encoder DSP example]","display_name":"DALI: a methodology for the co-design of dataflow applications on hardware/software architectures [video encoder DSP example]","publication_year":2004,"publication_date":"2004-01-24","ids":{"openalex":"https://openalex.org/W1597839615","doi":"https://doi.org/10.1109/sbcci.2003.1232811","mag":"1597839615"},"language":"en","primary_location":{"id":"doi:10.1109/sbcci.2003.1232811","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci.2003.1232811","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003178960","display_name":"M\u00e1rio V\u00e9stias","orcid":"https://orcid.org/0000-0001-8556-4507"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"M.P. Vestias","raw_affiliation_strings":["INESC-ID/IST, Lisboa, Portugal","INESC\u2010ID/IST, Lisboa, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID/IST, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"INESC\u2010ID/IST, Lisboa, Portugal","institution_ids":["https://openalex.org/I141596103"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062555847","display_name":"Hor\u00e1cio C. Neto","orcid":"https://orcid.org/0000-0002-3621-8322"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"H.C. Neto","raw_affiliation_strings":["INESC-ID/IST, Lisboa, Portugal","INESC\u2010ID/IST, Lisboa, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID/IST, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"INESC\u2010ID/IST, Lisboa, Portugal","institution_ids":["https://openalex.org/I141596103"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07433786,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"220","issue":null,"first_page":"85","last_page":"90"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7850029468536377},{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.7760652303695679},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6643997430801392},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6498509645462036},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.6445063352584839},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5742998719215393},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5581230521202087},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5465221405029297},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.49242103099823},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.45443597435951233},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4541064202785492},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.44400039315223694},{"id":"https://openalex.org/keywords/software-design","display_name":"Software design","score":0.4365207254886627},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.4123746156692505},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3801228106021881},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.28069302439689636},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.21092993021011353},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08473506569862366}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7850029468536377},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.7760652303695679},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6643997430801392},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6498509645462036},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.6445063352584839},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5742998719215393},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5581230521202087},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5465221405029297},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.49242103099823},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.45443597435951233},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4541064202785492},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.44400039315223694},{"id":"https://openalex.org/C52913732","wikidata":"https://www.wikidata.org/wiki/Q857102","display_name":"Software design","level":4,"score":0.4365207254886627},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.4123746156692505},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3801228106021881},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.28069302439689636},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.21092993021011353},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08473506569862366},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/sbcci.2003.1232811","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sbcci.2003.1232811","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5600000023841858}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1582450315","https://openalex.org/W1596752139","https://openalex.org/W1976417857","https://openalex.org/W2024060531","https://openalex.org/W2072358147","https://openalex.org/W2084825390","https://openalex.org/W2095409492","https://openalex.org/W2097911714","https://openalex.org/W2099736035","https://openalex.org/W2128286183","https://openalex.org/W2144018376","https://openalex.org/W2164123397","https://openalex.org/W2166720067","https://openalex.org/W3150544384","https://openalex.org/W4243459916"],"related_works":["https://openalex.org/W2164808568","https://openalex.org/W1937135962","https://openalex.org/W4240280328","https://openalex.org/W2166219277","https://openalex.org/W2073697740","https://openalex.org/W2137262315","https://openalex.org/W2088983481","https://openalex.org/W2146527276","https://openalex.org/W2535681959","https://openalex.org/W2510000542"],"abstract_inverted_index":{"The":[0,47,62],"design":[1,33,72],"of":[2,34,64,73],"dedicated":[3,35],"systems":[4],"is":[5,17,68],"subject":[6],"to":[7,29,52],"severe":[8],"cost,":[9],"performance,":[10],"time-to-market":[11],"and":[12,41],"flexibility":[13],"constraints.":[14],"So,":[15],"it":[16],"becoming":[18],"a":[19,26,58,74],"quite":[20],"complex":[21],"process.":[22],"This":[23],"paper":[24],"proposes":[25],"system-level":[27],"methodology":[28,48,67],"help":[30],"in":[31],"the":[32,50,54,65,71],"architectures,":[36],"possibly":[37],"with":[38,70],"both":[39],"hardware":[40],"software":[42],"components,":[43],"for":[44,57,76],"dataflow-dominated":[45],"applications.":[46],"helps":[49],"designer":[51],"find":[53],"best":[55],"architecture":[56],"particular":[59],"customer's":[60],"specification.":[61],"potential":[63],"proposed":[66],"illustrated":[69],"system":[75],"video":[77],"encoding.":[78]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
