{"id":"https://openalex.org/W2142944325","doi":"https://doi.org/10.1109/sasp.2010.5521138","title":"Design of a custom VEE core in a chip multiprocessor","display_name":"Design of a custom VEE core in a chip multiprocessor","publication_year":2010,"publication_date":"2010-06-01","ids":{"openalex":"https://openalex.org/W2142944325","doi":"https://doi.org/10.1109/sasp.2010.5521138","mag":"2142944325"},"language":"en","primary_location":{"id":"doi:10.1109/sasp.2010.5521138","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sasp.2010.5521138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE 8th Symposium on Application Specific Processors (SASP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060794953","display_name":"Dan Upton","orcid":"https://orcid.org/0000-0002-1456-7572"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Dan Upton","raw_affiliation_strings":["Department of Computer Science, University of Virginia, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Virginia, USA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046756907","display_name":"Kim Hazelwood","orcid":"https://orcid.org/0000-0002-2713-8507"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kim Hazelwood","raw_affiliation_strings":["Department of Computer Science, University of Virginia, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Virginia, USA","institution_ids":["https://openalex.org/I51556381"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5060794953"],"corresponding_institution_ids":["https://openalex.org/I51556381"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1744954,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"97","last_page":"100"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7889723777770996},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6627150177955627},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6301442980766296},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.5822071433067322},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5771069526672363},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5768117904663086},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5745159983634949},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.5700328350067139},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5326231122016907},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.47765958309173584},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47023648023605347},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4631796181201935},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3736559748649597},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3474690020084381},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.29456818103790283}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7889723777770996},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6627150177955627},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6301442980766296},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.5822071433067322},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5771069526672363},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5768117904663086},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5745159983634949},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.5700328350067139},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5326231122016907},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.47765958309173584},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47023648023605347},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4631796181201935},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3736559748649597},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3474690020084381},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.29456818103790283},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/sasp.2010.5521138","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sasp.2010.5521138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE 8th Symposium on Application Specific Processors (SASP)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.167.665","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.167.665","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.virginia.edu/%7Edsu9w/upton10design.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":50,"referenced_works":["https://openalex.org/W86243697","https://openalex.org/W1500546894","https://openalex.org/W1569551987","https://openalex.org/W1829813581","https://openalex.org/W1965351873","https://openalex.org/W2007920703","https://openalex.org/W2022740893","https://openalex.org/W2066444215","https://openalex.org/W2072737419","https://openalex.org/W2099708455","https://openalex.org/W2102727118","https://openalex.org/W2104225326","https://openalex.org/W2105528304","https://openalex.org/W2107138176","https://openalex.org/W2112085716","https://openalex.org/W2112243402","https://openalex.org/W2113167168","https://openalex.org/W2114809512","https://openalex.org/W2117115928","https://openalex.org/W2120230074","https://openalex.org/W2120274141","https://openalex.org/W2122963045","https://openalex.org/W2123022206","https://openalex.org/W2131847522","https://openalex.org/W2132100607","https://openalex.org/W2134633067","https://openalex.org/W2142892618","https://openalex.org/W2142919037","https://openalex.org/W2147943147","https://openalex.org/W2148865465","https://openalex.org/W2156858199","https://openalex.org/W2157074753","https://openalex.org/W2159449877","https://openalex.org/W2161992906","https://openalex.org/W2165006697","https://openalex.org/W2170653240","https://openalex.org/W3140903683","https://openalex.org/W3142147837","https://openalex.org/W3146783815","https://openalex.org/W4231002400","https://openalex.org/W4238973656","https://openalex.org/W4239813889","https://openalex.org/W4241410512","https://openalex.org/W4242466841","https://openalex.org/W4247264372","https://openalex.org/W4250692521","https://openalex.org/W6603516720","https://openalex.org/W6633991648","https://openalex.org/W6677520968","https://openalex.org/W6792941224"],"related_works":["https://openalex.org/W2326041751","https://openalex.org/W1547865754","https://openalex.org/W2276000909","https://openalex.org/W4250432526","https://openalex.org/W2101536355","https://openalex.org/W2171175484","https://openalex.org/W2085872434","https://openalex.org/W2562747857","https://openalex.org/W4308095153","https://openalex.org/W2026084820"],"abstract_inverted_index":{"Chip":[0],"multiprocessors":[1],"provide":[2],"an":[3,38],"opportunity":[4],"for":[5,21,41],"continuing":[6],"performance":[7,68,89,92],"growth":[8],"in":[9,74],"the":[10,17,35,72,91,101,124],"face":[11],"of":[12,37,63,76,93],"limited":[13],"single-thread":[14],"parallelism.":[15],"Although":[16],"best":[18],"design":[19,36],"path":[20],"such":[22],"chips":[23],"remains":[24],"open,":[25],"application-specific":[26,39],"core":[27,40,106],"designs":[28],"have":[29],"shown":[30],"promise.":[31],"This":[32],"work":[33],"considers":[34],"a":[42,49,56,61,128],"virtual":[43],"execution":[44],"environment.":[45],"We":[46,96],"use":[47],"Pin,":[48],"widely-used":[50],"dynamic":[51],"binary":[52],"instrumentation":[53],"system,":[54],"as":[55],"representative":[57],"process-level":[58],"VEE.":[59],"Through":[60],"combination":[62],"microarchitectural":[64],"simulation":[65],"and":[66,82,86,115],"hardware":[67],"counters,":[69],"we":[70],"profile":[71],"VEE":[73,102,126],"terms":[75],"cache":[77],"behavior,":[78,85],"functional":[79],"unit":[80],"usage,":[81],"branch":[83],"predictor":[84],"compare":[87],"its":[88],"to":[90,109,117],"benchmark":[94],"applications.":[95],"then":[97],"show":[98],"that":[99],"running":[100,123],"on":[103,127],"our":[104],"specialized":[105],"uses":[107],"up":[108,116],"15%":[110],"less":[111,119],"power":[112],"per":[113],"cycle":[114],"5%":[118],"energy":[120],"overall":[121],"than":[122],"same":[125],"general-purpose":[129],"core.":[130]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
