{"id":"https://openalex.org/W2159458033","doi":"https://doi.org/10.1109/sasp.2009.5226335","title":"Register Multimapping: A technique for reducing register bank conflicts in processors with large register files","display_name":"Register Multimapping: A technique for reducing register bank conflicts in processors with large register files","publication_year":2009,"publication_date":"2009-07-01","ids":{"openalex":"https://openalex.org/W2159458033","doi":"https://doi.org/10.1109/sasp.2009.5226335","mag":"2159458033"},"language":"en","primary_location":{"id":"doi:10.1109/sasp.2009.5226335","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sasp.2009.5226335","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE 7th Symposium on Application Specific Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002502787","display_name":"Nam Le Duong","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Nam Duong","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067547869","display_name":"Rakesh Kumar","orcid":"https://orcid.org/0000-0002-3290-2629"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rakesh Kumar","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, USA","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5002502787"],"corresponding_institution_ids":["https://openalex.org/I157725225"],"apc_list":null,"apc_paid":null,"fwci":0.2638,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.60996547,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"50","last_page":"53"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/register","display_name":"Register (sociolinguistics)","score":0.9223698377609253},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.9179670810699463},{"id":"https://openalex.org/keywords/processor-register","display_name":"Processor register","score":0.877083420753479},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7745299339294434},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.653830885887146},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.6057876348495483},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4808388650417328},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.39063316583633423},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2598861753940582},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.20877382159233093},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.14621052145957947},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10239559412002563},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.06894567608833313},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.061048150062561035}],"concepts":[{"id":"https://openalex.org/C2779235478","wikidata":"https://www.wikidata.org/wiki/Q286576","display_name":"Register (sociolinguistics)","level":2,"score":0.9223698377609253},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.9179670810699463},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.877083420753479},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7745299339294434},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.653830885887146},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.6057876348495483},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4808388650417328},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.39063316583633423},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2598861753940582},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.20877382159233093},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.14621052145957947},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10239559412002563},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.06894567608833313},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.061048150062561035},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/sasp.2009.5226335","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sasp.2009.5226335","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE 7th Symposium on Application Specific Processors","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W120460711","https://openalex.org/W1969714231","https://openalex.org/W2034147186","https://openalex.org/W2089363288","https://openalex.org/W2110263160","https://openalex.org/W2128221687","https://openalex.org/W2148662141","https://openalex.org/W4240046008","https://openalex.org/W4244495268","https://openalex.org/W4245021564"],"related_works":["https://openalex.org/W2159458033","https://openalex.org/W2078229301","https://openalex.org/W3117494601","https://openalex.org/W2169314615","https://openalex.org/W3013232686","https://openalex.org/W107804864","https://openalex.org/W2470887939","https://openalex.org/W4239499145","https://openalex.org/W2137413127","https://openalex.org/W2126420334"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"investigate":[4],"register":[5,12,19,32,71],"multimapping":[6,27],"as":[7],"a":[8],"technique":[9],"to":[10,33,38,79,94],"reduce":[11],"bank":[13,53],"conflicts":[14,56],"for":[15],"processors":[16,86,102],"with":[17],"large":[18],"files,":[20],"but":[21],"relatively":[22],"slow":[23],"clock":[24],"speeds.":[25],"Register":[26],"involves":[28],"mapping":[29],"an":[30],"architectural":[31],"multiple":[34],"physical":[35,48,65],"registers":[36],"belonging":[37],"different":[39],"banks.":[40],"Reads":[41],"can":[42,57,73],"proceed":[43],"using":[44],"any":[45],"of":[46,64,107],"the":[47],"registers,":[49],"thereby":[50],"minimizing":[51],"read":[52],"conflicts.":[54],"Write":[55],"be":[58],"minimized":[59],"by":[60],"allowing":[61],"delayed":[62,105],"allocation":[63,106],"registers.":[66,108],"Our":[67],"experiments":[68],"show":[69],"that":[70,87,103],"multi-mapping":[72],"result":[74],"in":[75],"performance":[76],"improvements":[77],"up":[78,93],"15%":[80],"(10%":[81],"on":[82,97],"average)":[83,98],"over":[84,99],"baseline":[85],"are":[88,92],"port":[89,100],"constrained.":[90],"Improvements":[91],"13%":[95],"(5.5%":[96],"constrained":[101],"support":[104]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}