{"id":"https://openalex.org/W2124889927","doi":"https://doi.org/10.1109/sasp.2008.4570782","title":"Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays","display_name":"Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays","publication_year":2008,"publication_date":"2008-06-01","ids":{"openalex":"https://openalex.org/W2124889927","doi":"https://doi.org/10.1109/sasp.2008.4570782","mag":"2124889927"},"language":"en","primary_location":{"id":"doi:10.1109/sasp.2008.4570782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sasp.2008.4570782","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Symposium on Application Specific Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/174616","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044467469","display_name":"Giovanni Ansaloni","orcid":"https://orcid.org/0000-0002-8940-3775"},"institutions":[{"id":"https://openalex.org/I57201433","display_name":"Universit\u00e0 della Svizzera italiana","ror":"https://ror.org/03c4atk17","country_code":"CH","type":"education","lineage":["https://openalex.org/I57201433"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Giovanni Ansaloni","raw_affiliation_strings":["Faculty of Informatics, University of Lugano, Lugano, Switzerland","Fac. of Inf., Univ. of Lugano, Lugano"],"affiliations":[{"raw_affiliation_string":"Faculty of Informatics, University of Lugano, Lugano, Switzerland","institution_ids":["https://openalex.org/I57201433"]},{"raw_affiliation_string":"Fac. of Inf., Univ. of Lugano, Lugano","institution_ids":["https://openalex.org/I57201433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022989275","display_name":"Paolo Bonzini","orcid":null},"institutions":[{"id":"https://openalex.org/I57201433","display_name":"Universit\u00e0 della Svizzera italiana","ror":"https://ror.org/03c4atk17","country_code":"CH","type":"education","lineage":["https://openalex.org/I57201433"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Paolo Bonzini","raw_affiliation_strings":["Faculty of Informatics, University of Lugano, Lugano, Switzerland","Fac. of Inf., Univ. of Lugano, Lugano"],"affiliations":[{"raw_affiliation_string":"Faculty of Informatics, University of Lugano, Lugano, Switzerland","institution_ids":["https://openalex.org/I57201433"]},{"raw_affiliation_string":"Fac. of Inf., Univ. of Lugano, Lugano","institution_ids":["https://openalex.org/I57201433"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001362973","display_name":"Laura Pozzi","orcid":"https://orcid.org/0000-0003-1083-8782"},"institutions":[{"id":"https://openalex.org/I57201433","display_name":"Universit\u00e0 della Svizzera italiana","ror":"https://ror.org/03c4atk17","country_code":"CH","type":"education","lineage":["https://openalex.org/I57201433"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Laura Pozzi","raw_affiliation_strings":["Faculty of Informatics, University of Lugano, Lugano, Switzerland","Fac. of Inf., Univ. of Lugano, Lugano"],"affiliations":[{"raw_affiliation_string":"Faculty of Informatics, University of Lugano, Lugano, Switzerland","institution_ids":["https://openalex.org/I57201433"]},{"raw_affiliation_string":"Fac. of Inf., Univ. of Lugano, Lugano","institution_ids":["https://openalex.org/I57201433"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5044467469"],"corresponding_institution_ids":["https://openalex.org/I57201433"],"apc_list":null,"apc_paid":null,"fwci":4.8223,"has_fulltext":false,"cited_by_count":31,"citation_normalized_percentile":{"value":0.95340746,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"26","last_page":"33"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7869029641151428},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.7636383771896362},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6891334056854248},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6546187400817871},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6059502363204956},{"id":"https://openalex.org/keywords/granularity","display_name":"Granularity","score":0.5975019335746765},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5577610731124878},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4581616520881653},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4491443932056427},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4211251735687256},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.42099729180336},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.41794389486312866},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35223376750946045},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3045896291732788},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10754996538162231}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7869029641151428},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.7636383771896362},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6891334056854248},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6546187400817871},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6059502363204956},{"id":"https://openalex.org/C177774035","wikidata":"https://www.wikidata.org/wiki/Q1246948","display_name":"Granularity","level":2,"score":0.5975019335746765},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5577610731124878},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4581616520881653},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4491443932056427},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4211251735687256},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.42099729180336},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.41794389486312866},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35223376750946045},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3045896291732788},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10754996538162231},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1109/sasp.2008.4570782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/sasp.2008.4570782","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 Symposium on Application Specific Processors","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.455.8084","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.455.8084","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.inf.usi.ch/faculty/pozzi/papers/sasp08.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.567.8937","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.567.8937","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.inf.usi.ch/file/pub/35/ansaloni-bonzini-pozzi-sasp08.pdf","raw_type":"text"},{"id":"pmh:oai:infoscience.epfl.ch:174616","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/174616","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},{"id":"pmh:oai:infoscience.tind.io:174616","is_oa":true,"landing_page_url":"https://infoscience.epfl.ch/handle/20.500.14299/77387","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"conference proceedings"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:174616","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/174616","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W201652765","https://openalex.org/W1493000054","https://openalex.org/W1502361557","https://openalex.org/W1532503506","https://openalex.org/W1686420892","https://openalex.org/W1974046032","https://openalex.org/W2007199485","https://openalex.org/W2010074783","https://openalex.org/W2034841960","https://openalex.org/W2039538849","https://openalex.org/W2083868341","https://openalex.org/W2105715355","https://openalex.org/W2113560252","https://openalex.org/W2117105306","https://openalex.org/W2135050419","https://openalex.org/W2137570657","https://openalex.org/W2165892109","https://openalex.org/W2169406908","https://openalex.org/W2544732887","https://openalex.org/W4230144752","https://openalex.org/W4234479839","https://openalex.org/W4250486818","https://openalex.org/W4254944975","https://openalex.org/W4285719527","https://openalex.org/W6630154184","https://openalex.org/W6637151178","https://openalex.org/W6811785195"],"related_works":["https://openalex.org/W4292829262","https://openalex.org/W1996820488","https://openalex.org/W2130825721","https://openalex.org/W1925985328","https://openalex.org/W3128899411","https://openalex.org/W1887481132","https://openalex.org/W2206000934","https://openalex.org/W4238593108","https://openalex.org/W2102547348","https://openalex.org/W2308099738"],"abstract_inverted_index":{"Reconfigurable":[0,48,84],"Arrays":[1,49],"combine":[2],"the":[3,66,104,143,146],"benefit":[4],"of":[5,9,14,25,65,68,77,90,93,136,142,145,154],"spatial":[6],"execution,":[7],"typical":[8],"hardware":[10],"solutions,":[11],"with":[12,95],"that":[13,129,158],"programmability,":[15],"present":[16],"in":[17],"microprocessors.":[18],"When":[19],"mapping":[20,125],"software":[21],"applications":[22,156],"(or":[23],"parts":[24],"them)":[26],"onto":[27],"hardware,":[28],"however,":[29],"FPGAs":[30],"often":[31],"provide":[32],"more":[33,171],"flexibility":[34],"than":[35,120],"is":[36,127],"needed,":[37],"and":[38,109],"do":[39],"not":[40],"implement":[41],"coarser-level":[42],"operations":[43],"efficiently.":[44],"Therefore,":[45],"Coarse":[46],"Grained":[47],"(CGRAs)":[50],"have":[51],"been":[52],"proposed":[53,128,147],"to":[54,101,133],"this":[55,71],"aim.":[56],"While":[57],"most":[58],"CGRA":[59,173],"designs":[60],"feature":[61],"an":[62,69,114],"array":[63],"cell":[64,88],"order":[67],"ALU,":[70],"paper":[72],"proposes":[73],"a":[74,87,91,121,134,152,164],"new":[75],"kind":[76],"coarse":[78],"grained":[79],"array,":[80],"called":[81],"EGRA":[82,99],"(Expression-Grained":[83],"Array),":[85],"featuring":[86],"composed":[89],"cluster":[92],"ALUs":[94],"flexible":[96],"interconnect.":[97],"The":[98],"attempts":[100],"further":[102],"close":[103],"performance":[105],"gap":[106],"between":[107],"reconfigurable":[108,165],"hardwired":[110],"logic":[111],"by":[112],"implementing":[113],"arithmetic/logic":[115],"expression":[116],"per":[117],"cell,":[118],"rather":[119],"single":[122],"operation.":[123],"A":[124],"methodology":[126],"can":[130,160],"retargetably":[131],"compile":[132],"family":[135],"EGRAs,":[137],"therefore":[138],"enabling":[139],"architectural":[140],"exploration":[141],"granularity":[144],"cell.":[148],"Performance":[149],"results":[150],"on":[151],"number":[153],"embedded":[155],"show":[157],"EGRAs":[159],"be":[161],"used":[162],"as":[163],"fabric":[166],"for":[167],"customizable":[168],"processors,":[169],"outperforming":[170],"traditional":[172],"designs.":[174]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":7}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}