{"id":"https://openalex.org/W2575106254","doi":"https://doi.org/10.1109/samos.2016.7818375","title":"An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures","display_name":"An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures","publication_year":2016,"publication_date":"2016-07-01","ids":{"openalex":"https://openalex.org/W2575106254","doi":"https://doi.org/10.1109/samos.2016.7818375","mag":"2575106254"},"language":"en","primary_location":{"id":"doi:10.1109/samos.2016.7818375","is_oa":false,"landing_page_url":"https://doi.org/10.1109/samos.2016.7818375","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049984593","display_name":"Efstathios Sotiriou-Xanthopoulos","orcid":"https://orcid.org/0000-0001-8323-3747"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Efstathios Sotiriou-Xanthopoulos","raw_affiliation_strings":["School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037614080","display_name":"Leonard Masing","orcid":"https://orcid.org/0000-0002-5745-4447"},"institutions":[{"id":"https://openalex.org/I102335020","display_name":"Karlsruhe Institute of Technology","ror":"https://ror.org/04t3en479","country_code":"DE","type":"education","lineage":["https://openalex.org/I102335020","https://openalex.org/I1305996414"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Leonard Masing","raw_affiliation_strings":["Institute for Information Processing, Karlsruhe Institute of Technology, Karlsruhe, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Information Processing, Karlsruhe Institute of Technology, Karlsruhe, Germany","institution_ids":["https://openalex.org/I102335020"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072486756","display_name":"Kostas Siozios","orcid":"https://orcid.org/0000-0002-0285-2202"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Kostas Siozios","raw_affiliation_strings":["School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089110665","display_name":"George Economakos","orcid":null},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"George Economakos","raw_affiliation_strings":["School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043131021","display_name":"Dimitrios Soudris","orcid":"https://orcid.org/0000-0002-6930-6847"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Dimitrios Soudris","raw_affiliation_strings":["School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024739574","display_name":"J\u00fcrgen Becker","orcid":"https://orcid.org/0000-0002-5082-5487"},"institutions":[{"id":"https://openalex.org/I102335020","display_name":"Karlsruhe Institute of Technology","ror":"https://ror.org/04t3en479","country_code":"DE","type":"education","lineage":["https://openalex.org/I102335020","https://openalex.org/I1305996414"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jurgen Becker","raw_affiliation_strings":["Institute for Information Processing, Karlsruhe Institute of Technology, Karlsruhe, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Information Processing, Karlsruhe Institute of Technology, Karlsruhe, Germany","institution_ids":["https://openalex.org/I102335020"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5049984593"],"corresponding_institution_ids":["https://openalex.org/I174458059"],"apc_list":null,"apc_paid":null,"fwci":0.3153,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.61030656,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"372","last_page":"377"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8578428030014038},{"id":"https://openalex.org/keywords/rapid-prototyping","display_name":"Rapid prototyping","score":0.6037937998771667},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5900163054466248},{"id":"https://openalex.org/keywords/virtual-prototyping","display_name":"Virtual prototyping","score":0.5600534081459045},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5507949590682983},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5262013077735901},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.523297131061554},{"id":"https://openalex.org/keywords/symmetric-multiprocessor-system","display_name":"Symmetric multiprocessor system","score":0.5160455703735352},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.514188289642334},{"id":"https://openalex.org/keywords/host","display_name":"Host (biology)","score":0.48774224519729614},{"id":"https://openalex.org/keywords/abstraction-layer","display_name":"Abstraction layer","score":0.4509918987751007},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4428868591785431},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.4336532950401306},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.38073107600212097},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.312857985496521},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.2996152639389038},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2066294252872467},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.09176656603813171}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8578428030014038},{"id":"https://openalex.org/C2780395129","wikidata":"https://www.wikidata.org/wiki/Q1128971","display_name":"Rapid prototyping","level":2,"score":0.6037937998771667},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5900163054466248},{"id":"https://openalex.org/C2780991453","wikidata":"https://www.wikidata.org/wiki/Q3408177","display_name":"Virtual prototyping","level":2,"score":0.5600534081459045},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5507949590682983},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5262013077735901},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.523297131061554},{"id":"https://openalex.org/C172430144","wikidata":"https://www.wikidata.org/wiki/Q17111997","display_name":"Symmetric multiprocessor system","level":2,"score":0.5160455703735352},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.514188289642334},{"id":"https://openalex.org/C126831891","wikidata":"https://www.wikidata.org/wiki/Q221673","display_name":"Host (biology)","level":2,"score":0.48774224519729614},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.4509918987751007},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4428868591785431},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.4336532950401306},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.38073107600212097},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.312857985496521},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2996152639389038},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2066294252872467},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.09176656603813171},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/samos.2016.7818375","is_oa":false,"landing_page_url":"https://doi.org/10.1109/samos.2016.7818375","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4399999976158142,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1968547622","https://openalex.org/W2082640993","https://openalex.org/W4233850144"],"related_works":["https://openalex.org/W2016877068","https://openalex.org/W2149166411","https://openalex.org/W2152989729","https://openalex.org/W1614428294","https://openalex.org/W1676660241","https://openalex.org/W65350138","https://openalex.org/W2115579040","https://openalex.org/W1565125589","https://openalex.org/W2133408453","https://openalex.org/W756858136"],"abstract_inverted_index":{"The":[0],"increasing":[1],"performance":[2],"and":[3,34,140],"power":[4],"requirements":[5],"in":[6,54,92],"embedded":[7],"systems":[8,64],"has":[9],"lead":[10],"to":[11,70,83,152,174,179],"a":[12,42,118,143,157],"variety":[13],"of":[14,22,50,60,73,77,101,159],"heterogeneous":[15],"hardware":[16,78,90,138],"architectures,":[17],"featuring":[18,57],"many":[19],"different":[20,58],"types":[21,59],"processing":[23],"elements.":[24],"This":[25,96],"heterogeneity":[26],"however":[27],"induces":[28],"extra":[29],"effort":[30],"on":[31],"system":[32,148],"development":[33],"programming.":[35],"To":[36],"address":[37],"this":[38,85],"heterogeneity,":[39],"OpenCL":[40,102,123,128,160],"provides":[41],"portable":[43],"programming":[44],"model":[45],"which":[46,114],"enables":[47,169],"the":[48,71,89,99,127,132,137,166],"use":[49],"one":[51],"source":[52],"code":[53],"various":[55],"architectures":[56],"processors.":[61],"Also,":[62],"such":[63],"impose":[65],"higher":[66,93],"design":[67,144],"complexity":[68],"due":[69],"existence":[72],"an":[74,108,122],"increased":[75],"number":[76],"components.":[79],"Virtual":[80,104],"Prototyping":[81],"aims":[82],"alleviate":[84],"issue":[86],"by":[87,106,130,172],"enabling":[88],"modeling":[91],"abstraction":[94],"levels.":[95],"paper":[97],"combines":[98],"benefits":[100],"with":[103,136],"Prototyping,":[105],"proposing":[107],"OpenCL-based":[109],"framework":[110,168],"for":[111,146],"rapid":[112],"prototyping,":[113],"(a)":[115],"automatically":[116],"derives":[117],"virtual":[119],"prototype":[120],"from":[121],"code;":[124],"(b)":[125],"executes":[126],"application":[129],"running":[131],"host":[133],"program":[134],"along":[135],"simulation;":[139],"(c)":[141],"proposes":[142],"flow":[145],"faster":[147,170],"evaluation,":[149],"as":[150,177],"compared":[151,178],"state-of-the-art":[153,180],"FPGA-based":[154],"flow.":[155,181],"Using":[156],"set":[158],"benchmarks,":[161],"it":[162],"is":[163],"shown":[164],"that":[165],"proposed":[167],"prototyping":[171],"up":[173],"18":[175],"x,":[176]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}