{"id":"https://openalex.org/W2220144261","doi":"https://doi.org/10.1109/samos.2015.7363665","title":"Efficient dual-ISA support in a retargetable, asynchronous Dynamic Binary Translator","display_name":"Efficient dual-ISA support in a retargetable, asynchronous Dynamic Binary Translator","publication_year":2015,"publication_date":"2015-07-01","ids":{"openalex":"https://openalex.org/W2220144261","doi":"https://doi.org/10.1109/samos.2015.7363665","mag":"2220144261"},"language":"en","primary_location":{"id":"doi:10.1109/samos.2015.7363665","is_oa":false,"landing_page_url":"https://doi.org/10.1109/samos.2015.7363665","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://www.research.ed.ac.uk/en/publications/5017a420-5ec5-4a6a-af51-5c577031c46a","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054308553","display_name":"Tom Spink","orcid":"https://orcid.org/0000-0002-7662-3146"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Tom Spink","raw_affiliation_strings":["Institute for Computing Systems Architecture, School of Informatics, University of Edinburgh, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Computing Systems Architecture, School of Informatics, University of Edinburgh, UK","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044205392","display_name":"Harry Wagstaff","orcid":"https://orcid.org/0000-0002-2079-8596"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Harry Wagstaff","raw_affiliation_strings":["Institute for Computing Systems Architecture, School of Informatics, University of Edinburgh, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Computing Systems Architecture, School of Informatics, University of Edinburgh, UK","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070407969","display_name":"Bj\u00f6rn Franke","orcid":"https://orcid.org/0000-0002-1219-8523"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Bj\u00f6rn Franke","raw_affiliation_strings":["Institute for Computing Systems Architecture, School of Informatics, University of Edinburgh, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Computing Systems Architecture, School of Informatics, University of Edinburgh, UK","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027477866","display_name":"Nigel Topham","orcid":"https://orcid.org/0000-0002-6310-0602"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Nigel Topham","raw_affiliation_strings":["Institute for Computing Systems Architecture, School of Informatics, University of Edinburgh, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Computing Systems Architecture, School of Informatics, University of Edinburgh, UK","institution_ids":["https://openalex.org/I98677209"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I98677209"],"apc_list":null,"apc_paid":null,"fwci":0.2041,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.41207503,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"103","last_page":"112"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8834360241889954},{"id":"https://openalex.org/keywords/binary-translation","display_name":"Binary translation","score":0.6825968623161316},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6279663443565369},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.6237867474555969},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5549842119216919},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5098547339439392},{"id":"https://openalex.org/keywords/spec#","display_name":"Spec#","score":0.4745638966560364},{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.46381041407585144},{"id":"https://openalex.org/keywords/arm-architecture","display_name":"ARM architecture","score":0.4572477340698242},{"id":"https://openalex.org/keywords/retargeting","display_name":"Retargeting","score":0.45151782035827637},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4359390437602997},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.42584678530693054},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.41746512055397034},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4140302538871765},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.41161268949508667},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4041227400302887},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.151201993227005}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8834360241889954},{"id":"https://openalex.org/C2778971978","wikidata":"https://www.wikidata.org/wiki/Q2287075","display_name":"Binary translation","level":3,"score":0.6825968623161316},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6279663443565369},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.6237867474555969},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5549842119216919},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5098547339439392},{"id":"https://openalex.org/C2778565505","wikidata":"https://www.wikidata.org/wiki/Q2207566","display_name":"Spec#","level":2,"score":0.4745638966560364},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.46381041407585144},{"id":"https://openalex.org/C26771161","wikidata":"https://www.wikidata.org/wiki/Q16980","display_name":"ARM architecture","level":2,"score":0.4572477340698242},{"id":"https://openalex.org/C2780575108","wikidata":"https://www.wikidata.org/wiki/Q7316652","display_name":"Retargeting","level":2,"score":0.45151782035827637},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4359390437602997},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.42584678530693054},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.41746512055397034},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4140302538871765},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.41161268949508667},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4041227400302887},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.151201993227005},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/samos.2015.7363665","is_oa":false,"landing_page_url":"https://doi.org/10.1109/samos.2015.7363665","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.ed.ac.uk:openaire/5017a420-5ec5-4a6a-af51-5c577031c46a","is_oa":true,"landing_page_url":"https://www.research.ed.ac.uk/en/publications/5017a420-5ec5-4a6a-af51-5c577031c46a","pdf_url":null,"source":{"id":"https://openalex.org/S4306400321","display_name":"Edinburgh Research Explorer (University of Edinburgh)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I98677209","host_organization_name":"University of Edinburgh","host_organization_lineage":["https://openalex.org/I98677209"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Spink, T, Wagstaff, H, Franke, B & Topham, N 2015, Efficient Dual-ISA Support in a Retargetable, Asynchronous Dynamic Binary Translator. in Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on. Institute of Electrical and Electronics Engineers, pp. 103 - 112. https://doi.org/10.1109/SAMOS.2015.7363665","raw_type":"contributionToPeriodical"},{"id":"pmh:oai:pure.ed.ac.uk:publications/5017a420-5ec5-4a6a-af51-5c577031c46a","is_oa":false,"landing_page_url":"https://www.research.ed.ac.uk/portal/en/publications/efficient-dualisa-support-in-a-retargetable-asynchronous-dynamic-binary-translator(5017a420-5ec5-4a6a-af51-5c577031c46a).html","pdf_url":null,"source":{"id":"https://openalex.org/S4406922455","display_name":"Edinburgh Research Explorer","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""}],"best_oa_location":{"id":"pmh:oai:pure.ed.ac.uk:openaire/5017a420-5ec5-4a6a-af51-5c577031c46a","is_oa":true,"landing_page_url":"https://www.research.ed.ac.uk/en/publications/5017a420-5ec5-4a6a-af51-5c577031c46a","pdf_url":null,"source":{"id":"https://openalex.org/S4306400321","display_name":"Edinburgh Research Explorer (University of Edinburgh)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I98677209","host_organization_name":"University of Edinburgh","host_organization_lineage":["https://openalex.org/I98677209"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Spink, T, Wagstaff, H, Franke, B & Topham, N 2015, Efficient Dual-ISA Support in a Retargetable, Asynchronous Dynamic Binary Translator. in Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on. Institute of Electrical and Electronics Engineers, pp. 103 - 112. https://doi.org/10.1109/SAMOS.2015.7363665","raw_type":"contributionToPeriodical"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G3632991813","display_name":null,"funder_award_id":"EP/I013539/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W1522250664","https://openalex.org/W1605940800","https://openalex.org/W1987805948","https://openalex.org/W1999421692","https://openalex.org/W2019326155","https://openalex.org/W2019828116","https://openalex.org/W2043785486","https://openalex.org/W2050289144","https://openalex.org/W2072737419","https://openalex.org/W2077103208","https://openalex.org/W2084767355","https://openalex.org/W2096218937","https://openalex.org/W2102570774","https://openalex.org/W2103604881","https://openalex.org/W2104225326","https://openalex.org/W2111569356","https://openalex.org/W2114086120","https://openalex.org/W2120635877","https://openalex.org/W2121945276","https://openalex.org/W2123022206","https://openalex.org/W2134559770","https://openalex.org/W2134633067","https://openalex.org/W2141711229","https://openalex.org/W2146878726","https://openalex.org/W2155104856","https://openalex.org/W2157074753","https://openalex.org/W2163935347","https://openalex.org/W3143191405","https://openalex.org/W4230686555","https://openalex.org/W4232036317","https://openalex.org/W4235822340","https://openalex.org/W4242550244","https://openalex.org/W4243006798","https://openalex.org/W4244854666","https://openalex.org/W4249170992"],"related_works":["https://openalex.org/W2510534818","https://openalex.org/W1990058210","https://openalex.org/W2115270696","https://openalex.org/W629804722","https://openalex.org/W1976377428","https://openalex.org/W2369102298","https://openalex.org/W2731280337","https://openalex.org/W1584408494","https://openalex.org/W3152269949","https://openalex.org/W2157797887"],"abstract_inverted_index":{"Dynamic":[0],"Binary":[1],"Translation":[2],"(DBT)":[3],"allows":[4],"software":[5,121],"compiled":[6,178],"for":[7,58,104,172,179,208],"one":[8,81],"Instruction":[9],"Set":[10],"Architecture":[11],"(ISA)":[12],"to":[13,79,88,169,187,198],"be":[14,77,129],"executed":[15,73],"on":[16,182],"a":[17,20,46,56,101,132,144,150],"processor":[18],"supporting":[19],"different":[21,47,78],"ISA.":[22],"Some":[23],"modern":[24],"DBT":[25,111,134,162],"systems":[26],"decouple":[27],"their":[28,89],"main":[29],"execution":[30,165],"loop":[31],"from":[32,149],"the":[33,39,68,71,80,84,137,173,190],"built-in":[34],"Just-In-Time":[35],"(JIT)":[36],"compiler,":[37],"i.e.":[38],"JIT":[40,85],"compiler":[41,86],"can":[42,128],"operate":[43],"asynchronously":[44],"in":[45,107,131,160],"thread":[48],"without":[49],"blocking":[50],"program":[51],"execution.":[52],"However,":[53],"this":[54,97,127],"creates":[55],"problem":[57],"target":[59,138],"architectures":[60],"with":[61],"dual-ISA":[62,105],"support":[63,106,159],"such":[64,108],"as":[65],"ARM/THUMB,":[66,180],"where":[67,136],"ISA":[69,115,139],"of":[70,120,167,189,192],"currently":[72],"instruction":[74,122],"stream":[75],"may":[76],"processed":[82],"by":[83],"due":[87],"decoupled":[90],"operation":[91],"and":[92,118,163,185,203],"dynamic":[93],"mode":[94,116],"changes.":[95],"In":[96],"paper":[98],"we":[99],"present":[100],"new":[102],"approach":[103],"an":[109],"asynchronous":[110],"system,":[112,135],"which":[113,194],"integrates":[114],"tracking":[117],"hot-swapping":[119],"decoders.":[123],"We":[124,154],"demonstrate":[125,164],"how":[126],"achieved":[130],"retargetable":[133],"is":[140,147],"not":[141],"hard-coded,":[142],"but":[143],"processor-specific":[145],"module":[146],"generated":[148],"high-level":[151],"architecture":[152],"description.":[153],"have":[155],"implemented":[156],"ARM":[157],"V5T":[158],"our":[161],"rates":[166],"up":[168,186],"1148":[170],"MIPS":[171],"SPEC":[174],"CPU":[175],"2006":[176],"benchmarks":[177],"achieving":[181],"average":[183],"192%,":[184],"323%,":[188],"speed":[191],"QEMU,":[193],"has":[195],"been":[196],"subject":[197],"intensive":[199],"manual":[200],"performance":[201],"tuning":[202],"requires":[204],"significant":[205],"low-level":[206],"effort":[207],"retargeting.":[209]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}