{"id":"https://openalex.org/W2016243737","doi":"https://doi.org/10.1109/samos.2013.6621114","title":"Mapping of PRP/HSR redundancy protocols onto a configurable FPGA/CPU based architecture","display_name":"Mapping of PRP/HSR redundancy protocols onto a configurable FPGA/CPU based architecture","publication_year":2013,"publication_date":"2013-07-01","ids":{"openalex":"https://openalex.org/W2016243737","doi":"https://doi.org/10.1109/samos.2013.6621114","mag":"2016243737"},"language":"en","primary_location":{"id":"doi:10.1109/samos.2013.6621114","is_oa":false,"landing_page_url":"https://doi.org/10.1109/samos.2013.6621114","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053753437","display_name":"Holger Flatt","orcid":null},"institutions":[{"id":"https://openalex.org/I4210111500","display_name":"Fraunhofer Institute of Optronics, System Technologies and Image Exploitation","ror":"https://ror.org/01zx97922","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210111500","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Holger Flatt","raw_affiliation_strings":["Fraunhofer IOSB-INA, Application Center Industrial Automation, Lemgo, Germany","Applic. Center Ind. Autom., Fraunhofer IOSB-INA, Lemgo, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fraunhofer IOSB-INA, Application Center Industrial Automation, Lemgo, Germany","institution_ids":["https://openalex.org/I4210111500"]},{"raw_affiliation_string":"Applic. Center Ind. Autom., Fraunhofer IOSB-INA, Lemgo, Germany","institution_ids":["https://openalex.org/I4210111500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025905769","display_name":"J\u00fcrgen Jasperneite","orcid":"https://orcid.org/0000-0001-7962-2491"},"institutions":[{"id":"https://openalex.org/I4210111500","display_name":"Fraunhofer Institute of Optronics, System Technologies and Image Exploitation","ror":"https://ror.org/01zx97922","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210111500","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jurgen Jasperneite","raw_affiliation_strings":["Fraunhofer IOSB-INA, Application Center Industrial Automation, Lemgo, Germany","Applic. Center Ind. Autom., Fraunhofer IOSB-INA, Lemgo, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fraunhofer IOSB-INA, Application Center Industrial Automation, Lemgo, Germany","institution_ids":["https://openalex.org/I4210111500"]},{"raw_affiliation_string":"Applic. Center Ind. Autom., Fraunhofer IOSB-INA, Lemgo, Germany","institution_ids":["https://openalex.org/I4210111500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065185983","display_name":"Daniel Dennstedt","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Daniel Dennstedt","raw_affiliation_strings":["Yacoub Automation GmbH, Berlin, Germany","Yacoub Autom. GmbH, Berlin, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Yacoub Automation GmbH, Berlin, Germany","institution_ids":[]},{"raw_affiliation_string":"Yacoub Autom. GmbH, Berlin, Germany","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088855056","display_name":"T D Hung","orcid":"https://orcid.org/0000-0001-5064-3029"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tran Dinh Hung","raw_affiliation_strings":["Yacoub Automation GmbH, Berlin, Germany","Yacoub Autom. GmbH, Berlin, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Yacoub Automation GmbH, Berlin, Germany","institution_ids":[]},{"raw_affiliation_string":"Yacoub Autom. GmbH, Berlin, Germany","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"8","issue":null,"first_page":"121","last_page":"128"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12216","display_name":"Network Time Synchronization Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12216","display_name":"Network Time Synchronization Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9954000115394592,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8101434707641602},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7522849440574646},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6615631580352783},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.5366330742835999},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5162539482116699},{"id":"https://openalex.org/keywords/master-clock","display_name":"Master clock","score":0.4875123202800751},{"id":"https://openalex.org/keywords/synchronizing","display_name":"Synchronizing","score":0.4806348383426666},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3830608129501343},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15833860635757446},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.09645339846611023}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8101434707641602},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7522849440574646},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6615631580352783},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.5366330742835999},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5162539482116699},{"id":"https://openalex.org/C65595194","wikidata":"https://www.wikidata.org/wiki/Q1000863","display_name":"Master clock","level":4,"score":0.4875123202800751},{"id":"https://openalex.org/C162932704","wikidata":"https://www.wikidata.org/wiki/Q1058791","display_name":"Synchronizing","level":3,"score":0.4806348383426666},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3830608129501343},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15833860635757446},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.09645339846611023},{"id":"https://openalex.org/C761482","wikidata":"https://www.wikidata.org/wiki/Q118093","display_name":"Transmission (telecommunications)","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/samos.2013.6621114","is_oa":false,"landing_page_url":"https://doi.org/10.1109/samos.2013.6621114","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)","raw_type":"proceedings-article"},{"id":"pmh:oai:publica.fraunhofer.de:publica/382006","is_oa":false,"landing_page_url":"https://publica.fraunhofer.de/handle/publica/382006","pdf_url":null,"source":{"id":"https://openalex.org/S4306400318","display_name":"Fraunhofer-Publica (Fraunhofer-Gesellschaft)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4923324","host_organization_name":"Fraunhofer-Gesellschaft","host_organization_lineage":["https://openalex.org/I4923324"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference paper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1602442476","https://openalex.org/W1971693622","https://openalex.org/W1985567175","https://openalex.org/W2031806949","https://openalex.org/W2045571631","https://openalex.org/W2051050718","https://openalex.org/W2051640123","https://openalex.org/W2161991185","https://openalex.org/W2746505796"],"related_works":["https://openalex.org/W2359328895","https://openalex.org/W2363535981","https://openalex.org/W2007402811","https://openalex.org/W2326762630","https://openalex.org/W2391354408","https://openalex.org/W1485756991","https://openalex.org/W2376218453","https://openalex.org/W2984236338","https://openalex.org/W2951566637","https://openalex.org/W2144994265"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,6,41,46,102,118,172,188],"mapping":[4],"of":[5,32,49,77,145],"seamless":[7,157],"redundancy":[8,158],"protocols":[9],"PRP":[10,152],"and":[11,35,80,132,153,167],"HSR":[12,154],"in":[13,140,151,183],"combination":[14],"with":[15],"IEEE":[16,36,134],"1588":[17,37,135],"based":[18,25],"clock":[19,136],"synchronization":[20],"onto":[21,40],"a":[22,43,68,81,91,156,162],"configurable":[23],"CPU/FPGA":[24],"Redundancy":[26],"Box":[27],"architecture.":[28],"Whereas":[29],"core":[30],"functions":[31],"PRP,":[33],"HSR,":[34],"are":[38,115,138],"mapped":[39],"FPGA,":[42],"CPU":[44],"executes":[45],"control":[47],"parts":[48],"these":[50],"protocols.":[51],"An":[52],"optional":[53],"attached":[54],"standard":[55],"switch":[56,84],"ASIC":[57],"provides":[58],"direct":[59],"connection":[60],"to":[61,121,185],"several":[62,149],"network":[63,166,169],"devices.":[64],"For":[65],"validation":[66],"purpose,":[67],"special":[69],"embedded":[70],"platform":[71],"is":[72,75,159],"proposed":[73],"that":[74,89],"composed":[76],"an":[78,133,143],"FPGA":[79,96,119],"commercial":[82],"off-the-shelf":[83],"ASIC.":[85],"The":[86],"results":[87],"show":[88],"even":[90],"low-cost":[92],"Altera":[93],"Cyclone":[94],"IV":[95],"comprising":[97],"74,000":[98],"logic":[99],"elements":[100],"fulfills":[101],"requirements":[103],"for":[104,161],"protocol":[105],"processing":[106],"at":[107],"100":[108],"Mbps":[109],"per":[110],"port.":[111],"Minimum":[112],"size":[113],"frames":[114],"forwarded":[116],"by":[117],"up":[120],"two":[122],"times":[123],"faster":[124],"than":[125],"competitive":[126],"implementations.":[127],"Three":[128],"connected":[129],"PRP/HSR":[130],"RedBoxes":[131,150],"master":[137],"synchronizing":[139],"laboratory":[141],"within":[142],"accuracy":[144],"30":[146],"ns.":[147],"Using":[148],"mode,":[155],"demonstrated":[160],"PROFINET":[163],"RT":[164],"test":[165],"supplemental":[168],"components.":[170],"Overall,":[171],"presented":[173],"RedBox":[174],"can":[175],"be":[176],"flexibly":[177],"integrated":[178],"into":[179],"time-synchronized":[180],"industrial":[181],"networks":[182],"order":[184],"significantly":[186],"increase":[187],"communication":[189],"reliability.":[190]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}