{"id":"https://openalex.org/W2145653634","doi":"https://doi.org/10.1109/samos.2011.6045468","title":"On-chip network resource management design and validation","display_name":"On-chip network resource management design and validation","publication_year":2011,"publication_date":"2011-07-01","ids":{"openalex":"https://openalex.org/W2145653634","doi":"https://doi.org/10.1109/samos.2011.6045468","mag":"2145653634"},"language":"en","primary_location":{"id":"doi:10.1109/samos.2011.6045468","is_oa":false,"landing_page_url":"https://doi.org/10.1109/samos.2011.6045468","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082281016","display_name":"Francesco Bruschi","orcid":"https://orcid.org/0000-0001-5669-2788"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Francesco Bruschi","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","Dipartimento di Elettronica e Informazione Politecnico Di Milano"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione Politecnico Di Milano","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031451381","display_name":"Antonio Miele","orcid":"https://orcid.org/0000-0003-3197-0723"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Antonio Miele","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","Dipartimento di Elettronica e Informazione Politecnico Di Milano"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione Politecnico Di Milano","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062883620","display_name":"Vincenzo Rana","orcid":"https://orcid.org/0000-0001-6851-1737"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Vincenzo Rana","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","Dipartimento di Elettronica e Informazione Politecnico Di Milano"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione Politecnico Di Milano","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5082281016"],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":0.7002,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.74228022,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"4","issue":null,"first_page":"249","last_page":"254"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.800585150718689},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7876143455505371},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.737813413143158},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6004586219787598},{"id":"https://openalex.org/keywords/variety","display_name":"Variety (cybernetics)","score":0.5462971329689026},{"id":"https://openalex.org/keywords/resource","display_name":"Resource (disambiguation)","score":0.5264689922332764},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5038427710533142},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.46900129318237305},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4404558539390564},{"id":"https://openalex.org/keywords/resource-management","display_name":"Resource management (computing)","score":0.41976457834243774},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.411072313785553},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3593432903289795},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.26926934719085693},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.0781944990158081}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.800585150718689},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7876143455505371},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.737813413143158},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6004586219787598},{"id":"https://openalex.org/C136197465","wikidata":"https://www.wikidata.org/wiki/Q1729295","display_name":"Variety (cybernetics)","level":2,"score":0.5462971329689026},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.5264689922332764},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5038427710533142},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.46900129318237305},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4404558539390564},{"id":"https://openalex.org/C2780609101","wikidata":"https://www.wikidata.org/wiki/Q17156588","display_name":"Resource management (computing)","level":2,"score":0.41976457834243774},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.411072313785553},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3593432903289795},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.26926934719085693},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0781944990158081},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/samos.2011.6045468","is_oa":false,"landing_page_url":"https://doi.org/10.1109/samos.2011.6045468","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/637314","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/637314","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.49000000953674316,"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1496267491","https://openalex.org/W1963638851","https://openalex.org/W1975010174","https://openalex.org/W1998537609","https://openalex.org/W2007545650","https://openalex.org/W2079527947","https://openalex.org/W2095211124","https://openalex.org/W2112865131","https://openalex.org/W2114026576","https://openalex.org/W2116793508","https://openalex.org/W2127919083","https://openalex.org/W2152099665","https://openalex.org/W2159001247","https://openalex.org/W2168072991","https://openalex.org/W4234461876","https://openalex.org/W6629762304","https://openalex.org/W6649844963"],"related_works":["https://openalex.org/W1976012348","https://openalex.org/W2560375935","https://openalex.org/W2614713859","https://openalex.org/W2002682434","https://openalex.org/W4387782849","https://openalex.org/W2137671689","https://openalex.org/W2144357574","https://openalex.org/W4230458348","https://openalex.org/W1966325333","https://openalex.org/W3198758847"],"abstract_inverted_index":{"Designing":[0],"interconnection":[1,77],"networks":[2,122],"for":[3,116,139],"systems":[4],"on-a-chip":[5],"is":[6],"getting":[7],"more":[8,58,60,152,166],"complex":[9,121],"due":[10],"to":[11,26,40,51,75,88,94,97,110,157],"the":[12,21,31,62,68,99,104,112,117,132,140,148,158,162],"increasing":[13],"number":[14],"and":[15,28,33,36,59,74,82,155,160],"heterogeneity":[16],"of":[17,23,44,53,64,71,119,134,143,150,164],"elements":[18],"they":[19,38,92],"connect,":[20],"variety":[22],"technologies":[24],"adopted":[25],"transmit":[27],"route":[29],"information,":[30],"performance":[32],"cost":[34],"requirements":[35],"constraints":[37],"have":[39,93,123],"satisfy.":[41],"The":[42],"complexity":[43],"such":[45,90,120],"transmission":[46],"fabrics":[47,78],"gets":[48],"then":[49],"closer":[50],"that":[52],"telecommunication":[54],"networks.":[55],"Designers":[56],"face":[57],"often":[61],"possibility":[63,133],"importing":[65],"techniques":[66],"from":[67],"classical":[69],"world":[70],"communication":[72],"networks,":[73],"augment":[76],"with":[79,147,161],"reconfigurable":[80,144],"features":[81],"dynamic":[83],"resource":[84],"management.":[85],"In":[86,127],"order":[87],"evaluate":[89],"opportunities,":[91],"be":[95],"able":[96],"simulate":[98],"architectures":[100],"in":[101],"mind":[102],"under":[103],"most":[105],"realistic":[106,153],"possible":[107],"conditions.":[108],"Up":[109],"now,":[111],"only":[113],"tools":[114],"exploited":[115],"simulation":[118,137],"been":[124],"network":[125],"simulators.":[126],"this":[128],"paper":[129],"we":[130],"consider":[131],"using":[135],"MPSoC":[136],"frameworks":[138],"early":[141],"evaluation":[142],"networks-on-chip":[145],"(NoCs),":[146],"advantage":[149],"providing":[151],"scenarios":[154],"stimuli":[156],"network,":[159],"aim":[163],"obtaining":[165],"reliable":[167],"evaluations.":[168]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}