{"id":"https://openalex.org/W2070854370","doi":"https://doi.org/10.1109/rtas.2014.6925992","title":"Hiding memory latency using fixed priority scheduling","display_name":"Hiding memory latency using fixed priority scheduling","publication_year":2014,"publication_date":"2014-04-01","ids":{"openalex":"https://openalex.org/W2070854370","doi":"https://doi.org/10.1109/rtas.2014.6925992","mag":"2070854370"},"language":"en","primary_location":{"id":"doi:10.1109/rtas.2014.6925992","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rtas.2014.6925992","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044172546","display_name":"Saud Wasly","orcid":"https://orcid.org/0000-0002-3827-4096"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]},{"id":"https://openalex.org/I185163786","display_name":"King Abdulaziz University","ror":"https://ror.org/02ma4wv74","country_code":"SA","type":"education","lineage":["https://openalex.org/I185163786"]}],"countries":["CA","SA"],"is_corresponding":true,"raw_author_name":"Saud Wasly","raw_affiliation_strings":["King Abdulaziz University, Saudi Arabia","University of Waterloo, Canada"],"affiliations":[{"raw_affiliation_string":"King Abdulaziz University, Saudi Arabia","institution_ids":["https://openalex.org/I185163786"]},{"raw_affiliation_string":"University of Waterloo, Canada","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009578055","display_name":"Rodolfo Pellizzoni","orcid":"https://orcid.org/0000-0002-7331-804X"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Rodolfo Pellizzoni","raw_affiliation_strings":["University of Waterloo, Canada"],"affiliations":[{"raw_affiliation_string":"University of Waterloo, Canada","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5044172546"],"corresponding_institution_ids":["https://openalex.org/I151746483","https://openalex.org/I185163786"],"apc_list":null,"apc_paid":null,"fwci":3.9842,"has_fulltext":false,"cited_by_count":29,"citation_normalized_percentile":{"value":0.93861983,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"75","last_page":"86"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8864461183547974},{"id":"https://openalex.org/keywords/uniprocessor-system","display_name":"Uniprocessor system","score":0.7331674098968506},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5780429840087891},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5277510285377502},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4965284466743469},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4943506717681885},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.4729803800582886},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4378676414489746},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4143734276294708},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.4021451473236084},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.29807159304618835},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.22082862257957458},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.17882925271987915},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.14431339502334595},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.13819319009780884}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8864461183547974},{"id":"https://openalex.org/C79189994","wikidata":"https://www.wikidata.org/wiki/Q3488021","display_name":"Uniprocessor system","level":3,"score":0.7331674098968506},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5780429840087891},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5277510285377502},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4965284466743469},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4943506717681885},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.4729803800582886},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4378676414489746},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4143734276294708},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.4021451473236084},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.29807159304618835},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.22082862257957458},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.17882925271987915},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.14431339502334595},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.13819319009780884},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/rtas.2014.6925992","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rtas.2014.6925992","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W117356634","https://openalex.org/W1986904046","https://openalex.org/W2011497488","https://openalex.org/W2028665553","https://openalex.org/W2047686596","https://openalex.org/W2061663604","https://openalex.org/W2108024087","https://openalex.org/W2109172228","https://openalex.org/W2118378639","https://openalex.org/W2122833539","https://openalex.org/W2122969894","https://openalex.org/W2144856846","https://openalex.org/W2162528816","https://openalex.org/W2167631583","https://openalex.org/W3141273430"],"related_works":["https://openalex.org/W2021050177","https://openalex.org/W232296991","https://openalex.org/W2186708011","https://openalex.org/W2134237474","https://openalex.org/W2899110000","https://openalex.org/W3044927936","https://openalex.org/W2039391036","https://openalex.org/W2149154914","https://openalex.org/W2106200299","https://openalex.org/W2285316324"],"abstract_inverted_index":{"Modern":[0],"embedded":[1],"platforms":[2],"contain":[3],"a":[4,25,109,114],"variety":[5],"of":[6,24,82,105,116],"physical":[7,36],"resources,":[8],"such":[9],"as":[10],"caches,":[11],"interconnects,":[12],"main":[13,64,103],"memory,":[14],"etc.,":[15],"which":[16],"the":[17,22],"processor":[18,30,83,100,123,150],"must":[19],"access":[20,48,69],"during":[21],"execution":[23,32,60,126],"task.":[26],"We":[27,145],"argue":[28],"that":[29,77,120,147],"task":[31,59],"and":[33,61,124,157],"accesses":[34,62],"to":[35,44,63,66,88,127,138,154],"resources":[37],"should":[38],"be":[39,79,136],"co-scheduled":[40],"in":[41,52,97],"real-time":[42,118],"systems":[43,73],"predictably":[45],"hide":[46,67,89,128],"resource":[47],"latency.":[49,70,131],"In":[50],"particular,":[51],"this":[53,85,106],"work":[54],"we":[55,148],"focus":[56],"on":[57],"co-scheduling":[58],"memory":[65,90,129],"DRAM":[68],"Since":[71],"modern":[72],"implement":[74],"DMA":[75,95,125],"controllers":[76],"can":[78,135],"operated":[80],"independently":[81],"execution,":[84],"allows":[86],"us":[87],"transfer":[91,96,130],"latency":[92],"by":[93],"scheduling":[94,111],"parallel":[98],"with":[99],"execution.":[101],"The":[102,132],"contribution":[104],"paper":[107],"is":[108],"dynamic":[110],"algorithm":[112,134],"for":[113],"set":[115],"sporadic":[117],"tasks":[119],"efficiently":[121],"co-schedules":[122],"proposed":[133],"applied":[137],"either":[139],"uniprocessor":[140],"or":[141],"partitioned":[142],"multiprocessor":[143],"systems.":[144,160],"demonstrate":[146],"improve":[149],"utilization":[151],"significantly":[152],"compared":[153],"existing":[155],"scratchpad":[156],"cache":[158],"management":[159]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
