{"id":"https://openalex.org/W4407378099","doi":"https://doi.org/10.1109/rsp64122.2024.10871064","title":"Enhancing the VTR Flow: Integration of ABC9 via Yosys for Better Technology Mapping and Optimization","display_name":"Enhancing the VTR Flow: Integration of ABC9 via Yosys for Better Technology Mapping and Optimization","publication_year":2024,"publication_date":"2024-10-03","ids":{"openalex":"https://openalex.org/W4407378099","doi":"https://doi.org/10.1109/rsp64122.2024.10871064"},"language":"en","primary_location":{"id":"doi:10.1109/rsp64122.2024.10871064","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp64122.2024.10871064","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 International Workshop on Rapid System Prototyping (RSP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5099339955","display_name":"Navid Jafarof","orcid":"https://orcid.org/0009-0000-7504-1243"},"institutions":[{"id":"https://openalex.org/I106938459","display_name":"University of New Brunswick","ror":"https://ror.org/05nkf0n29","country_code":"CA","type":"education","lineage":["https://openalex.org/I106938459"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Navid Jafarof","raw_affiliation_strings":["University of New Brunswick,Faculty of Computer Science,Fredericton,Canada"],"affiliations":[{"raw_affiliation_string":"University of New Brunswick,Faculty of Computer Science,Fredericton,Canada","institution_ids":["https://openalex.org/I106938459"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067605823","display_name":"Kenneth B. Kent","orcid":"https://orcid.org/0000-0003-2764-823X"},"institutions":[{"id":"https://openalex.org/I106938459","display_name":"University of New Brunswick","ror":"https://ror.org/05nkf0n29","country_code":"CA","type":"education","lineage":["https://openalex.org/I106938459"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Kenneth B. Kent","raw_affiliation_strings":["University of New Brunswick,Faculty of Computer Science,Fredericton,Canada"],"affiliations":[{"raw_affiliation_string":"University of New Brunswick,Faculty of Computer Science,Fredericton,Canada","institution_ids":["https://openalex.org/I106938459"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5099339955"],"corresponding_institution_ids":["https://openalex.org/I106938459"],"apc_list":null,"apc_paid":null,"fwci":0.3706,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.69983276,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"56","last_page":"62"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11159","display_name":"Manufacturing Process and Optimization","score":0.48249998688697815,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11159","display_name":"Manufacturing Process and Optimization","score":0.48249998688697815,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6151171922683716},{"id":"https://openalex.org/keywords/flow","display_name":"Flow (mathematics)","score":0.4597679674625397},{"id":"https://openalex.org/keywords/human\u2013computer-interaction","display_name":"Human\u2013computer interaction","score":0.34598973393440247},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12167108058929443}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6151171922683716},{"id":"https://openalex.org/C38349280","wikidata":"https://www.wikidata.org/wiki/Q1434290","display_name":"Flow (mathematics)","level":2,"score":0.4597679674625397},{"id":"https://openalex.org/C107457646","wikidata":"https://www.wikidata.org/wiki/Q207434","display_name":"Human\u2013computer interaction","level":1,"score":0.34598973393440247},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12167108058929443},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/rsp64122.2024.10871064","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp64122.2024.10871064","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 International Workshop on Rapid System Prototyping (RSP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320319980","display_name":"New Brunswick Innovation Foundation","ror":"https://ror.org/02rbgnh75"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1528837436","https://openalex.org/W1635819215","https://openalex.org/W2005602803","https://openalex.org/W2007701500","https://openalex.org/W2063406991","https://openalex.org/W2139637699","https://openalex.org/W2168493238","https://openalex.org/W2591922920","https://openalex.org/W2949216549","https://openalex.org/W2950533501","https://openalex.org/W2988212920","https://openalex.org/W3007581096","https://openalex.org/W3033033241","https://openalex.org/W4214717370","https://openalex.org/W4368232696","https://openalex.org/W4379115958","https://openalex.org/W6681822247"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W4391913857","https://openalex.org/W2358668433","https://openalex.org/W4396701345","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W4396696052"],"abstract_inverted_index":{"This":[0],"study":[1],"optimizes":[2],"the":[3,43,56,88,91,101],"Verilog-to-Routing":[4],"(VTR)":[5],"flow,":[6],"an":[7],"open-source":[8],"Computer-Aided":[9],"Design":[10],"(CAD)":[11],"tool.":[12],"It":[13],"utilizes":[14],"ODIN":[15],"II":[16],"and":[17,25,28,33,51,54,72,97],"Parmys":[18],"for":[19,22,30,60,77],"synthesis,":[20],"ABC":[21,58],"technology":[23,49],"mapping,":[24],"Versatile":[26],"Place":[27],"Route":[29],"packing,":[31],"placement,":[32],"routing.":[34],"The":[35],"ABC9":[36],"optimizations,":[37],"integrated":[38],"as":[39],"a":[40,74],"pass":[41],"within":[42],"Yosys":[44],"Open":[45],"Synthesis":[46],"Suite,":[47],"enhance":[48],"mapping":[50],"optimization":[52],"stages":[53],"outperform":[55],"traditional":[57],"tool":[59],"large,":[61],"complex":[62],"designs.":[63],"These":[64],"optimizations":[65],"improve":[66],"timing":[67],"behavior":[68],"in":[69],"multi-clock":[70],"designs":[71],"include":[73],"delay":[75],"model":[76],"Field":[78],"Programmable":[79],"Gate":[80],"Array":[81],"(FPGA)":[82],"hard":[83,104],"blocks.":[84,105],"Various":[85],"benchmarks":[86],"assess":[87],"effectiveness":[89],"of":[90,103],"workflow":[92],"across":[93],"different":[94],"design":[95],"complexities":[96],"FPGA":[98],"architectures,":[99],"including":[100],"utilization":[102]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-03-04T09:10:02.777135","created_date":"2025-10-10T00:00:00"}