{"id":"https://openalex.org/W4321637075","doi":"https://doi.org/10.1109/rsp57251.2022.10039002","title":"Machine Learning-Based Hard/Soft Logic Trade-offs in VTR","display_name":"Machine Learning-Based Hard/Soft Logic Trade-offs in VTR","publication_year":2022,"publication_date":"2022-10-13","ids":{"openalex":"https://openalex.org/W4321637075","doi":"https://doi.org/10.1109/rsp57251.2022.10039002"},"language":"en","primary_location":{"id":"doi:10.1109/rsp57251.2022.10039002","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/rsp57251.2022.10039002","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Workshop on Rapid System Prototyping (RSP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056964468","display_name":"Ritwik Sinha","orcid":"https://orcid.org/0000-0002-0344-1368"},"institutions":[{"id":"https://openalex.org/I155417937","display_name":"Hochschule Bonn-Rhein-Sieg","ror":"https://ror.org/04m2anh63","country_code":"DE","type":"education","lineage":["https://openalex.org/I155417937"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Ritwik Sinha","raw_affiliation_strings":["Hochshule Bonn-Rhein-Sieg,Department of Computer Science,Sankt Augustin,Germany","Department of Computer Science, Hochshule Bonn-Rhein-Sieg, Sankt Augustin, Germany"],"affiliations":[{"raw_affiliation_string":"Hochshule Bonn-Rhein-Sieg,Department of Computer Science,Sankt Augustin,Germany","institution_ids":["https://openalex.org/I155417937"]},{"raw_affiliation_string":"Department of Computer Science, Hochshule Bonn-Rhein-Sieg, Sankt Augustin, Germany","institution_ids":["https://openalex.org/I155417937"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066861397","display_name":"Seyed Alireza Damghani","orcid":"https://orcid.org/0000-0002-0858-4632"},"institutions":[{"id":"https://openalex.org/I106938459","display_name":"University of New Brunswick","ror":"https://ror.org/05nkf0n29","country_code":"CA","type":"education","lineage":["https://openalex.org/I106938459"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Seyed Alireza Damghani","raw_affiliation_strings":["University of New Brunswick,Faculty of Computer Science,Fredericton,Canada","Faculty of Computer Science, University of New Brunswick, Fredericton, Canada"],"affiliations":[{"raw_affiliation_string":"University of New Brunswick,Faculty of Computer Science,Fredericton,Canada","institution_ids":["https://openalex.org/I106938459"]},{"raw_affiliation_string":"Faculty of Computer Science, University of New Brunswick, Fredericton, Canada","institution_ids":["https://openalex.org/I106938459"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067605823","display_name":"Kenneth B. Kent","orcid":"https://orcid.org/0000-0003-2764-823X"},"institutions":[{"id":"https://openalex.org/I106938459","display_name":"University of New Brunswick","ror":"https://ror.org/05nkf0n29","country_code":"CA","type":"education","lineage":["https://openalex.org/I106938459"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Kenneth B. Kent","raw_affiliation_strings":["University of New Brunswick,Faculty of Computer Science,Fredericton,Canada","Faculty of Computer Science, University of New Brunswick, Fredericton, Canada"],"affiliations":[{"raw_affiliation_string":"University of New Brunswick,Faculty of Computer Science,Fredericton,Canada","institution_ids":["https://openalex.org/I106938459"]},{"raw_affiliation_string":"Faculty of Computer Science, University of New Brunswick, Fredericton, Canada","institution_ids":["https://openalex.org/I106938459"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5056964468"],"corresponding_institution_ids":["https://openalex.org/I155417937"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.19141677,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"57","last_page":"63"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9919000267982483,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9879999756813049,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8548907041549683},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6151411533355713},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.5363596081733704},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5123056173324585},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4797976315021515},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.45310941338539124},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38580507040023804},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35175108909606934},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2688441276550293},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.17483937740325928}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8548907041549683},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6151411533355713},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.5363596081733704},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5123056173324585},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4797976315021515},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.45310941338539124},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38580507040023804},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35175108909606934},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2688441276550293},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.17483937740325928}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/rsp57251.2022.10039002","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/rsp57251.2022.10039002","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE International Workshop on Rapid System Prototyping (RSP)","raw_type":"proceedings-article"},{"id":"pmh:oai:pub.h-brs.de:6628","is_oa":false,"landing_page_url":"https://pub.h-brs.de/frontdoor/index/index/docId/6628","pdf_url":null,"source":{"id":"https://openalex.org/S4306400385","display_name":"Publication Server of Bonn-Rhein-Sieg University of Applied Sciences (Bonn-Rhein-Sieg University of Applied Sciences)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I135140700","host_organization_name":"University of Bonn","host_organization_lineage":["https://openalex.org/I135140700"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2022 IEEE International Workshop on Rapid System Prototyping (RSP), 13 October 2022, Shanghai, China","raw_type":"doc-type:conferenceobject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.49000000953674316,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W2009537245","https://openalex.org/W2101234009","https://openalex.org/W2138383740","https://openalex.org/W2484065175","https://openalex.org/W2490662969","https://openalex.org/W2523362988","https://openalex.org/W2623293810","https://openalex.org/W2981891337","https://openalex.org/W3033033241","https://openalex.org/W3033506121","https://openalex.org/W3091995083","https://openalex.org/W3094974974","https://openalex.org/W4211035621","https://openalex.org/W4240402958"],"related_works":["https://openalex.org/W2004826944","https://openalex.org/W2544421437","https://openalex.org/W2792739143","https://openalex.org/W2029330513","https://openalex.org/W2583559879","https://openalex.org/W3045607100","https://openalex.org/W2178815085","https://openalex.org/W2369375926","https://openalex.org/W1901384934","https://openalex.org/W1595048679"],"abstract_inverted_index":{"Circuit":[0],"optimization,":[1],"in":[2,192,208],"any":[3],"application,":[4],"is":[5,86,96],"of":[6,16,25,40,68,142,202,216],"high":[7],"importance":[8],"since":[9],"it":[10,196],"not":[11],"only":[12],"improves":[13],"the":[14,17,23,26,31,37,41,66,97,102,112,117,131,140,143,167,181,193,209],"efficiency":[15],"intended":[18],"purpose":[19],"but":[20],"also":[21],"enhances":[22],"quality":[24],"final":[27],"product.":[28],"It":[29],"enables":[30],"circuit":[32,44],"designer":[33],"to":[34,36,46,50,70,116,138,153,159,212],"cater":[35],"specific":[38],"needs":[39],"customer.":[42],"For":[43],"optimization":[45],"occur,":[47],"we":[48],"need":[49,168],"elaborate":[51],"these":[52],"circuits":[53],"on":[54,148,163,174],"a":[55],"primary":[56],"level":[57,201],"and":[58,120,172],"perform":[59],"synthesis":[60,155],"operations.":[61],"Previous":[62],"research":[63],"shows":[64],"that":[65,100,129],"investigation":[67],"improvements":[69],"different":[71],"Hardware":[72],"Description":[73],"Language":[74],"(HDL)":[75],"elaboration":[76],"phases,":[77],"was":[78],"completely":[79],"closed":[80],"source.":[81],"Verilog":[82],"To":[83,128],"Routing":[84],"(VTR)":[85],"an":[87,205],"open-source":[88],"Electronic":[89],"Design":[90],"Automation":[91],"(EDA)":[92],"tool.":[93],"ODIN":[94],"II":[95],"VTR":[98,210],"synthesizer":[99],"parses":[101],"input":[103],"Verilog,":[104],"elaborates":[105],"its":[106],"Abstract":[107],"Syntax":[108],"Tree":[109],"(AST),":[110],"performs":[111,121],"partial":[113],"mapping":[114],"according":[115],"architecture":[118],"file,":[119],"optimizations":[122],"such":[123],"as":[124],"unused":[125],"logic":[126,135],"removal.":[127],"end,":[130],"hard":[132],"versus":[133],"soft":[134],"trade-off":[136],"aims":[137,197],"optimize":[139],"performance":[141],"circuit.":[144,194],"This":[145,178],"project":[146],"focuses":[147],"using":[149],"machine":[150],"learning":[151],"approaches":[152],"make":[154,213],"tools":[156],"intelligent":[157],"enough":[158],"decide":[160],"this":[161,200,217],"ratio":[162],"their":[164],"own,":[165],"without":[166],"for":[169,183],"human":[170],"intervention,":[171],"based":[173],"some":[175],"predefined":[176],"criteria.":[177],"paper":[179],"discusses":[180],"criteria":[182],"having":[184],"less":[185,188],"latency":[186],"or":[187],"critical":[189],"path":[190],"delay":[191],"Also,":[195],"at":[198,204],"providing":[199],"intelligence":[203],"earlier":[206],"stage":[207],"pipeline":[211],"better":[214],"use":[215],"information.":[218]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
