{"id":"https://openalex.org/W4285346926","doi":"https://doi.org/10.1109/rsp53691.2021.9806222","title":"Prototyping FPGA through overlays","display_name":"Prototyping FPGA through overlays","publication_year":2021,"publication_date":"2021-10-14","ids":{"openalex":"https://openalex.org/W4285346926","doi":"https://doi.org/10.1109/rsp53691.2021.9806222"},"language":"en","primary_location":{"id":"doi:10.1109/rsp53691.2021.9806222","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp53691.2021.9806222","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Workshop on Rapid System Prototyping (RSP)","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048077564","display_name":"Th\u00e9otime Bollengier","orcid":"https://orcid.org/0009-0006-7315-2736"},"institutions":[{"id":"https://openalex.org/I161929037","display_name":"Universit\u00e9 de Bretagne Occidentale","ror":"https://ror.org/01b8h3982","country_code":"FR","type":"education","lineage":["https://openalex.org/I161929037"]},{"id":"https://openalex.org/I4210123702","display_name":"Laboratoire des Sciences et Techniques de l\u2019Information de la Communication et de la Connaissance","ror":"https://ror.org/0266kfd37","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I180375564","https://openalex.org/I201181511","https://openalex.org/I205703379","https://openalex.org/I2802204017","https://openalex.org/I4210123702","https://openalex.org/I4210127572","https://openalex.org/I4210145102","https://openalex.org/I4210148559","https://openalex.org/I4210159245","https://openalex.org/I4405260085"]},{"id":"https://openalex.org/I4210148559","display_name":"\u00c9cole nationale sup\u00e9rieure de techniques avanc\u00e9es Bretagne","ror":"https://ror.org/059n54003","country_code":"FR","type":"education","lineage":["https://openalex.org/I201181511","https://openalex.org/I4210145102","https://openalex.org/I4210148559"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Theotime Bollengier","raw_affiliation_strings":["ENSTA Bretagne,Lab-STICC, UMR 6523,Brest,France","Lab-STICC_ARCAD - Equipe Hardware ARchitectures and CAD tools (France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENSTA Bretagne,Lab-STICC, UMR 6523,Brest,France","institution_ids":["https://openalex.org/I161929037","https://openalex.org/I4210123702","https://openalex.org/I4210148559"]},{"raw_affiliation_string":"Lab-STICC_ARCAD - Equipe Hardware ARchitectures and CAD tools (France)","institution_ids":["https://openalex.org/I161929037"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061188155","display_name":"Lo\u00efc Lagadec","orcid":"https://orcid.org/0000-0003-3778-3144"},"institutions":[{"id":"https://openalex.org/I161929037","display_name":"Universit\u00e9 de Bretagne Occidentale","ror":"https://ror.org/01b8h3982","country_code":"FR","type":"education","lineage":["https://openalex.org/I161929037"]},{"id":"https://openalex.org/I4210123702","display_name":"Laboratoire des Sciences et Techniques de l\u2019Information de la Communication et de la Connaissance","ror":"https://ror.org/0266kfd37","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I180375564","https://openalex.org/I201181511","https://openalex.org/I205703379","https://openalex.org/I2802204017","https://openalex.org/I4210123702","https://openalex.org/I4210127572","https://openalex.org/I4210145102","https://openalex.org/I4210148559","https://openalex.org/I4210159245","https://openalex.org/I4405260085"]},{"id":"https://openalex.org/I4210148559","display_name":"\u00c9cole nationale sup\u00e9rieure de techniques avanc\u00e9es Bretagne","ror":"https://ror.org/059n54003","country_code":"FR","type":"education","lineage":["https://openalex.org/I201181511","https://openalex.org/I4210145102","https://openalex.org/I4210148559"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Loic Lagadec","raw_affiliation_strings":["ENSTA Bretagne,Lab-STICC, UMR 6523,Brest,France","Lab-STICC_ARCAD - Equipe Hardware ARchitectures and CAD tools (France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENSTA Bretagne,Lab-STICC, UMR 6523,Brest,France","institution_ids":["https://openalex.org/I161929037","https://openalex.org/I4210123702","https://openalex.org/I4210148559"]},{"raw_affiliation_string":"Lab-STICC_ARCAD - Equipe Hardware ARchitectures and CAD tools (France)","institution_ids":["https://openalex.org/I161929037"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062908084","display_name":"Ciprian Teodorov","orcid":"https://orcid.org/0000-0002-0722-5857"},"institutions":[{"id":"https://openalex.org/I161929037","display_name":"Universit\u00e9 de Bretagne Occidentale","ror":"https://ror.org/01b8h3982","country_code":"FR","type":"education","lineage":["https://openalex.org/I161929037"]},{"id":"https://openalex.org/I4210123702","display_name":"Laboratoire des Sciences et Techniques de l\u2019Information de la Communication et de la Connaissance","ror":"https://ror.org/0266kfd37","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I180375564","https://openalex.org/I201181511","https://openalex.org/I205703379","https://openalex.org/I2802204017","https://openalex.org/I4210123702","https://openalex.org/I4210127572","https://openalex.org/I4210145102","https://openalex.org/I4210148559","https://openalex.org/I4210159245","https://openalex.org/I4405260085"]},{"id":"https://openalex.org/I4210148559","display_name":"\u00c9cole nationale sup\u00e9rieure de techniques avanc\u00e9es Bretagne","ror":"https://ror.org/059n54003","country_code":"FR","type":"education","lineage":["https://openalex.org/I201181511","https://openalex.org/I4210145102","https://openalex.org/I4210148559"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Ciprian Teodorov","raw_affiliation_strings":["ENSTA Bretagne,Lab-STICC, UMR 6523,Brest,France","Lab-STICC_P4S - Equipe Processes for Safe and Secure Software and Systems (France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENSTA Bretagne,Lab-STICC, UMR 6523,Brest,France","institution_ids":["https://openalex.org/I161929037","https://openalex.org/I4210123702","https://openalex.org/I4210148559"]},{"raw_affiliation_string":"Lab-STICC_P4S - Equipe Processes for Safe and Secure Software and Systems (France)","institution_ids":["https://openalex.org/I161929037"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.20097864,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"15","last_page":"21"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7090749740600586},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.6788930892944336},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6641066670417786},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5120868682861328},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4408004581928253},{"id":"https://openalex.org/keywords/rapid-prototyping","display_name":"Rapid prototyping","score":0.41288337111473083},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2693803906440735},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11872971057891846}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7090749740600586},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.6788930892944336},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6641066670417786},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5120868682861328},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4408004581928253},{"id":"https://openalex.org/C2780395129","wikidata":"https://www.wikidata.org/wiki/Q1128971","display_name":"Rapid prototyping","level":2,"score":0.41288337111473083},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2693803906440735},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11872971057891846},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/rsp53691.2021.9806222","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp53691.2021.9806222","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Workshop on Rapid System Prototyping (RSP)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-03761788v1","is_oa":false,"landing_page_url":"https://ensta.hal.science/hal-03761788","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2021 IEEE International Workshop on Rapid System Prototyping (RSP), Oct 2021, Paris, France. pp.15-21, ⟨10.1109/RSP53691.2021.9806222⟩","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1497161204","https://openalex.org/W1528837436","https://openalex.org/W1669114967","https://openalex.org/W2014316444","https://openalex.org/W2035847677","https://openalex.org/W2138383740","https://openalex.org/W2139637699","https://openalex.org/W2150022482","https://openalex.org/W2504919933","https://openalex.org/W2554510265","https://openalex.org/W2583746861","https://openalex.org/W2592947564","https://openalex.org/W2621788798","https://openalex.org/W2785649635","https://openalex.org/W2788424169","https://openalex.org/W2957361546","https://openalex.org/W3015998244","https://openalex.org/W3027559990","https://openalex.org/W3103838789","https://openalex.org/W3119486426","https://openalex.org/W3130402546","https://openalex.org/W3135674751","https://openalex.org/W6637097397","https://openalex.org/W6724499246"],"related_works":["https://openalex.org/W595346907","https://openalex.org/W153296825","https://openalex.org/W598989511","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"EFPGAs":[0],"give":[1],"designers":[2],"the":[3,12,18,72,77,85],"flexibility":[4],"to":[5,62,70,98],"make":[6],"changes":[7],"at":[8],"any":[9],"point":[10,67],"in":[11,17,80],"chip’s":[13],"life":[14],"span,":[15],"even":[16],"customers’":[19],"systems.":[20],"Though,":[21],"eFPGA":[22,39],"are":[23],"not":[24],"efficient":[25],"from":[26,50],"an":[27,38,99],"integration":[28,58],"perspective,":[29],"making":[30],"proper":[31],"dimensionning":[32],"and":[33,43,93,108],"tailoring":[34],"mandatory.":[35],"Unfortunately,":[36],"designing":[37],"is":[40,68],"a":[41],"complex":[42,60],"error-prone":[44],"task.":[45],"Even":[46],"though":[47],"automatic":[48],"generation":[49],"high":[51],"level":[52],"models":[53],"can":[54],"produce":[55],"correct-by-construction":[56],"layouts,":[57],"remains":[59],"due":[61],"process":[63],"variation.":[64],"A":[65],"key":[66],"then":[69],"reduce":[71],"technology":[73],"dependency.This":[74],"paper":[75],"presents":[76],"ELNATH":[78],"project":[79],"which":[81],"three":[82],"implementations":[83],"of":[84],"same":[86],"architecture":[87],"have":[88],"been":[89],"addressed:":[90],"overlay,":[91],"eFPGA,":[92],"55":[94],"nm":[95],"FPGA":[96],"thanks":[97],"open-source":[100],"integrated":[101],"tool":[102],"flow":[103],"that":[104],"supports":[105],"defining,":[106],"implementing":[107],"programming":[109],"reconfigurable":[110],"architectures.":[111]},"counts_by_year":[],"updated_date":"2026-07-02T09:51:11.867554","created_date":"2025-10-10T00:00:00"}