{"id":"https://openalex.org/W3095772072","doi":"https://doi.org/10.1109/rsp51120.2020.9244852","title":"(System)Verilog to Chisel Translation for Faster Hardware Design","display_name":"(System)Verilog to Chisel Translation for Faster Hardware Design","publication_year":2020,"publication_date":"2020-09-24","ids":{"openalex":"https://openalex.org/W3095772072","doi":"https://doi.org/10.1109/rsp51120.2020.9244852","mag":"3095772072"},"language":"en","primary_location":{"id":"doi:10.1109/rsp51120.2020.9244852","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp51120.2020.9244852","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 International Workshop on Rapid System Prototyping (RSP)","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053962337","display_name":"Jean Bruant","orcid":"https://orcid.org/0000-0001-8151-0392"},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Jean Bruant","raw_affiliation_strings":["OVHcloud, Paris, France","TIMA, Univ. Grenoble Alpes, CNRS, Grenoble INP1, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"OVHcloud, Paris, France","institution_ids":[]},{"raw_affiliation_string":"TIMA, Univ. Grenoble Alpes, CNRS, Grenoble INP1, Grenoble, France","institution_ids":["https://openalex.org/I106785703","https://openalex.org/I899635006","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090846025","display_name":"Pierre-Henri Horrein","orcid":"https://orcid.org/0000-0002-9714-7871"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Pierre-Henri Horrein","raw_affiliation_strings":["OVHcloud, Lyon, France"],"affiliations":[{"raw_affiliation_string":"OVHcloud, Lyon, France","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103105107","display_name":"Olivier Muller","orcid":"https://orcid.org/0000-0002-4182-0502"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]},{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Olivier Muller","raw_affiliation_strings":["TIMA, Univ. Grenoble Alpes, CNRS, Grenoble INP1, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"TIMA, Univ. Grenoble Alpes, CNRS, Grenoble INP1, Grenoble, France","institution_ids":["https://openalex.org/I106785703","https://openalex.org/I899635006","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072914891","display_name":"Tristan Grol\u00e9at","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tristan Groleat","raw_affiliation_strings":["OVHcloud, Brest, France"],"affiliations":[{"raw_affiliation_string":"OVHcloud, Brest, France","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113546155","display_name":"Frederic Petrot","orcid":null},"institutions":[{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]},{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Frederic Petrot","raw_affiliation_strings":["TIMA, Univ. Grenoble Alpes, CNRS, Grenoble INP1, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"TIMA, Univ. Grenoble Alpes, CNRS, Grenoble INP1, Grenoble, France","institution_ids":["https://openalex.org/I106785703","https://openalex.org/I899635006","https://openalex.org/I1294671590"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5053962337"],"corresponding_institution_ids":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I899635006"],"apc_list":null,"apc_paid":null,"fwci":0.4713,"has_fulltext":true,"cited_by_count":2,"citation_normalized_percentile":{"value":0.62131679,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"9","issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.8775045871734619},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8027380108833313},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6174060702323914},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.5664249062538147},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.5590589642524719},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5407301187515259},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.49612197279930115},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4610006809234619},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4297443926334381}],"concepts":[{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.8775045871734619},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8027380108833313},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6174060702323914},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5664249062538147},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.5590589642524719},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5407301187515259},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.49612197279930115},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4610006809234619},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4297443926334381},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/rsp51120.2020.9244852","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp51120.2020.9244852","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 International Workshop on Rapid System Prototyping (RSP)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-02949112v1","is_oa":false,"landing_page_url":"https://hal.science/hal-02949112","pdf_url":null,"source":{"id":"https://openalex.org/S4406922461","display_name":"SPIRE - Sciences Po Institutional REpository","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2020 31th International Symposium on Rapid System Prototyping (RSP), Sep 2020, VIrtual Conference, France","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5199999809265137,"id":"https://metadata.un.org/sdg/10","display_name":"Reduced inequalities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1983394510","https://openalex.org/W2045864241","https://openalex.org/W2072750798","https://openalex.org/W2106962797","https://openalex.org/W2127859789","https://openalex.org/W2170909854","https://openalex.org/W2318354022","https://openalex.org/W2598631327","https://openalex.org/W2612093424","https://openalex.org/W2771610171","https://openalex.org/W2801748224","https://openalex.org/W4240172596","https://openalex.org/W6735214697","https://openalex.org/W6737776912"],"related_works":["https://openalex.org/W3004362061","https://openalex.org/W2364622490","https://openalex.org/W2383986884","https://openalex.org/W2356141508","https://openalex.org/W4297665406","https://openalex.org/W2749962643","https://openalex.org/W2387264083","https://openalex.org/W2390807153","https://openalex.org/W2042515040","https://openalex.org/W2111408175"],"abstract_inverted_index":{"Bringing":[0],"agility":[1],"to":[2,39,72,83,86,96,111],"hardware":[3,11,18,42,91],"developments":[4],"has":[5],"been":[6],"a":[7,74,94,133,148],"long-running":[8],"goal":[9],"for":[10,60,117],"communities":[12],"struggling":[13],"with":[14,44,128],"limitations":[15],"of":[16,132],"current":[17],"description":[19],"languages":[20],"such":[21,32],"as":[22,33,93,114,140,142],"(System)Verilog":[23,110],"or":[24,66],"VHDL.":[25],"The":[26],"numerous":[27],"recent":[28],"Hardware":[29],"Construction":[30],"Languages":[31],"Chisel":[34,112],"are":[35,54],"providing":[36],"enhanced":[37],"ways":[38],"design":[40,137],"complex":[41,98],"architectures":[43],"notable":[45],"academic":[46],"and":[47,57,76,151],"industrial":[48],"successes.":[49],"While":[50],"the":[51,125,152],"latter":[52],"environments":[53],"now":[55],"mature":[56],"perfectly":[58],"suited":[59],"brand":[61],"new":[62],"projects,":[63],"migrating":[64],"partially":[65],"entirely":[67],"existing":[68,90],"Verilog":[69,146],"code-base":[70],"proves":[71],"be":[73,84],"challenging":[75],"very":[77],"time-consuming":[78],"process.":[79],"Successful":[80],"migrations":[81],"need":[82],"able":[85],"leverage":[87],"finely":[88],"tuned":[89],"descriptions":[92],"basis":[95],"build":[97],"systems":[99],"through":[100],"simple":[101],"iterations.":[102],"This":[103],"article":[104],"introduces":[105],"sv2chisel,":[106],"an":[107],"open-source":[108,145],"automated":[109],"translator":[113],"entry":[115],"point":[116],"this":[118],"iterative":[119],"migration":[120],"processes.":[121],"Our":[122],"tool":[123],"achieved":[124],"proper":[126],"translation,":[127],"on-par":[129],"resource":[130],"usage":[131],"real-world":[134],"production":[135],"FPGA":[136],"at":[138],"OVHcloud":[139],"well":[141],"two":[143],"independent":[144],"projects:":[147],"MIPS":[149],"core":[150,156],"size-optimized":[153],"32-bit":[154],"RISC-V":[155],"PicoRV32.":[157]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}