{"id":"https://openalex.org/W2912231221","doi":"https://doi.org/10.1109/rsp.2018.8631990","title":"Vicilogic 2.0: Online Learning and Prototyping of Digital Systems Using PYNQ-Z1/-Z2 SoC","display_name":"Vicilogic 2.0: Online Learning and Prototyping of Digital Systems Using PYNQ-Z1/-Z2 SoC","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2912231221","doi":"https://doi.org/10.1109/rsp.2018.8631990","mag":"2912231221"},"language":"en","primary_location":{"id":"doi:10.1109/rsp.2018.8631990","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp.2018.8631990","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Symposium on Rapid System Prototyping (RSP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101528289","display_name":"Fearghal Morgan","orcid":null},"institutions":[{"id":"https://openalex.org/I188760350","display_name":"Ollscoil na Gaillimhe \u2013 University of Galway","ror":"https://ror.org/03bea9k73","country_code":"IE","type":"education","lineage":["https://openalex.org/I188760350"]}],"countries":["IE"],"is_corresponding":true,"raw_author_name":"Fearghal Morgan","raw_affiliation_strings":["National University of Ireland, Galway"],"affiliations":[{"raw_affiliation_string":"National University of Ireland, Galway","institution_ids":["https://openalex.org/I188760350"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041575416","display_name":"Declan O\u2019Loughlin","orcid":"https://orcid.org/0000-0002-4521-0082"},"institutions":[{"id":"https://openalex.org/I188760350","display_name":"Ollscoil na Gaillimhe \u2013 University of Galway","ror":"https://ror.org/03bea9k73","country_code":"IE","type":"education","lineage":["https://openalex.org/I188760350"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Declan O'Loughlin","raw_affiliation_strings":["National University of Ireland, Galway"],"affiliations":[{"raw_affiliation_string":"National University of Ireland, Galway","institution_ids":["https://openalex.org/I188760350"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003183018","display_name":"Jeremy Audiger","orcid":null},"institutions":[{"id":"https://openalex.org/I188760350","display_name":"Ollscoil na Gaillimhe \u2013 University of Galway","ror":"https://ror.org/03bea9k73","country_code":"IE","type":"education","lineage":["https://openalex.org/I188760350"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Jeremy Audiger","raw_affiliation_strings":["National University of Ireland, Galway"],"affiliations":[{"raw_affiliation_string":"National University of Ireland, Galway","institution_ids":["https://openalex.org/I188760350"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019257313","display_name":"Yohan Boyer","orcid":null},"institutions":[{"id":"https://openalex.org/I188760350","display_name":"Ollscoil na Gaillimhe \u2013 University of Galway","ror":"https://ror.org/03bea9k73","country_code":"IE","type":"education","lineage":["https://openalex.org/I188760350"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Yohan Boyer","raw_affiliation_strings":["National University of Ireland, Galway"],"affiliations":[{"raw_affiliation_string":"National University of Ireland, Galway","institution_ids":["https://openalex.org/I188760350"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016594379","display_name":"Niall Timlin-Canning","orcid":null},"institutions":[{"id":"https://openalex.org/I188760350","display_name":"Ollscoil na Gaillimhe \u2013 University of Galway","ror":"https://ror.org/03bea9k73","country_code":"IE","type":"education","lineage":["https://openalex.org/I188760350"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Niall Timlin-Canning","raw_affiliation_strings":["National University of Ireland, Galway"],"affiliations":[{"raw_affiliation_string":"National University of Ireland, Galway","institution_ids":["https://openalex.org/I188760350"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074444574","display_name":"Krzysztof K\u0229pa","orcid":"https://orcid.org/0000-0003-0702-9570"},"institutions":[{"id":"https://openalex.org/I188760350","display_name":"Ollscoil na Gaillimhe \u2013 University of Galway","ror":"https://ror.org/03bea9k73","country_code":"IE","type":"education","lineage":["https://openalex.org/I188760350"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Krzysztof Kepa","raw_affiliation_strings":["National University of Ireland, Galway"],"affiliations":[{"raw_affiliation_string":"National University of Ireland, Galway","institution_ids":["https://openalex.org/I188760350"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030783014","display_name":"Seamus Cawley","orcid":null},"institutions":[{"id":"https://openalex.org/I188760350","display_name":"Ollscoil na Gaillimhe \u2013 University of Galway","ror":"https://ror.org/03bea9k73","country_code":"IE","type":"education","lineage":["https://openalex.org/I188760350"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Seamus Cawley","raw_affiliation_strings":["National University of Ireland, Galway"],"affiliations":[{"raw_affiliation_string":"National University of Ireland, Galway","institution_ids":["https://openalex.org/I188760350"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008791651","display_name":"Ian Gallivan","orcid":null},"institutions":[{"id":"https://openalex.org/I188760350","display_name":"Ollscoil na Gaillimhe \u2013 University of Galway","ror":"https://ror.org/03bea9k73","country_code":"IE","type":"education","lineage":["https://openalex.org/I188760350"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Ian Gallivan","raw_affiliation_strings":["National University of Ireland, Galway"],"affiliations":[{"raw_affiliation_string":"National University of Ireland, Galway","institution_ids":["https://openalex.org/I188760350"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040404208","display_name":"L\u00e1szl\u00f3 Bak\u00f3","orcid":"https://orcid.org/0000-0003-3295-5437"},"institutions":[{"id":"https://openalex.org/I43886","display_name":"Sapientia Hungarian University of Transylvania","ror":"https://ror.org/04ahh4d11","country_code":"RO","type":"education","lineage":["https://openalex.org/I43886"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Laszlo Bako","raw_affiliation_strings":["Sapientia Hungarian University of Transylvania"],"affiliations":[{"raw_affiliation_string":"Sapientia Hungarian University of Transylvania","institution_ids":["https://openalex.org/I43886"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020509977","display_name":"Frank Callaly","orcid":"https://orcid.org/0009-0006-8562-0648"},"institutions":[{"id":"https://openalex.org/I188760350","display_name":"Ollscoil na Gaillimhe \u2013 University of Galway","ror":"https://ror.org/03bea9k73","country_code":"IE","type":"education","lineage":["https://openalex.org/I188760350"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Frank Callaly","raw_affiliation_strings":["National University of Ireland, Galway"],"affiliations":[{"raw_affiliation_string":"National University of Ireland, Galway","institution_ids":["https://openalex.org/I188760350"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5101528289"],"corresponding_institution_ids":["https://openalex.org/I188760350"],"apc_list":null,"apc_paid":null,"fwci":1.0285,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.82590999,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":97},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9907000064849854,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.982699990272522,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7510225772857666},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6225807666778564},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5077379941940308},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.4947795271873474},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4434283673763275},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4274788796901703},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.41995131969451904},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3530811071395874}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7510225772857666},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6225807666778564},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5077379941940308},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.4947795271873474},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4434283673763275},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4274788796901703},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.41995131969451904},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3530811071395874}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/rsp.2018.8631990","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp.2018.8631990","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Symposium on Rapid System Prototyping (RSP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6499999761581421,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1971547752","https://openalex.org/W2011792419","https://openalex.org/W2056693943","https://openalex.org/W2541431377","https://openalex.org/W2797052609"],"related_works":["https://openalex.org/W2387264083","https://openalex.org/W2604877941","https://openalex.org/W2390885485","https://openalex.org/W1761969858","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2391854357","https://openalex.org/W2381510423","https://openalex.org/W4238487776"],"abstract_inverted_index":{"This":[0,97],"paper":[1,178],"presents":[2],"viciLogic":[3,45,69,163,181],"2.0,":[4],"a":[5,30,202,208],"scalable,":[6],"distributed":[7],"online":[8,59,194],"learning,":[9],"hardware":[10,40,65,77,171],"prototyping,":[11,66],"client":[12,103,190,209],"application":[13,191,210],"and":[14,81,85,94,105,125,139,146,162,165,174,193,207],"course":[15,110,121,195,204],"creator":[16],"platform":[17,73],"for":[18,119],"System":[19],"on":[20],"Chip":[21],"(SoC)-based":[22],"digital":[23,63],"systems.":[24],"User":[25],"applications":[26,104,199],"transparently":[27],"link":[28],"to":[29,151],"device":[31],"in":[32,41,141],"an":[33],"array":[34],"of":[35,89,101],"Xilinx":[36,53],"PYNQ-Zl":[37],"or-Z2":[38],"SoC":[39,62,115,156,170,185],"the":[42,52,87,99,148,169,180],"cloud.":[43],"The":[44,72,128,143,177],"prototype":[46,129,186],"builder":[47,130,144,187],"toolsuite":[48],"(which":[49],"integrates":[50,155],"with":[51,67,215],"Vivado":[54],"industry-standard":[55],"EDA":[56],"tools)":[57],"automates":[58],"(and":[60],"local)":[61],"logic":[64],"integrated":[68],"user":[70,76,91,126],"interface.":[71],"supports":[74],"real-time":[75],"input":[78],"signal":[79,83,116,153],"control":[80],"automated":[82],"control,":[84],"probes":[86],"state":[88,117],"all":[90],"design":[92,175],"internal":[93],"output":[95],"signals.":[96],"enables":[98],"creation":[100],"responsive":[102],"smart":[106],"browser-based":[107],"courses.":[108],"Online":[109],"functions":[111],"include":[112],"guided":[113],"lessons,":[114],"monitoring":[118],"automatic":[120],"progression,":[122],"knowledge":[123],"checks,":[124],"sandbox.":[127],"uses":[131],"source":[132],"VHDL":[133],"or":[134],"Verilog":[135],"projects":[136],"created,":[137],"simulated":[138],"synthesised":[140],"Vivado.":[142],"parses":[145],"modifies":[147],"HDL":[149],"model":[150],"provide":[152],"observability,":[154],"resources":[157],"(ARM,":[158],"AXI":[159],"interconnect,":[160],"peripherals":[161],"IP),":[164],"(using":[166],"Vivado)":[167],"generates":[168],"configuration":[172],"bitstream":[173],"metadata.":[176],"describes":[179],"2.0":[182],"server":[183],"architecture,":[184],"tool":[188],"flow,":[189],"creator,":[192],"creator.":[196],"Two":[197],"demonstration":[198],"are":[200],"presented,":[201],"counter":[203],"lesson":[205],"step":[206],"(16-bit":[211],"single":[212],"cycle":[213],"computer,":[214],"IDE).":[216]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":4},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}