{"id":"https://openalex.org/W2290845170","doi":"https://doi.org/10.1109/rsp.2015.7416548","title":"Dynamic data flow analysis for NoC based application synthesis","display_name":"Dynamic data flow analysis for NoC based application synthesis","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W2290845170","doi":"https://doi.org/10.1109/rsp.2015.7416548","mag":"2290845170"},"language":"en","primary_location":{"id":"doi:10.1109/rsp.2015.7416548","is_oa":false,"landing_page_url":"http://doi.org/10.1109/rsp.2015.7416548","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Symposium on Rapid System Prototyping (RSP)","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025896815","display_name":"Matthieu Payet","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Matthieu Payet","raw_affiliation_strings":["Univ. de Saint-Etienne, Saint-Etienne, France"],"affiliations":[{"raw_affiliation_string":"Univ. de Saint-Etienne, Saint-Etienne, France","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106744281","display_name":"Virginie Fresse","orcid":"https://orcid.org/0000-0002-9944-0174"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Virginie Fresse","raw_affiliation_strings":["Univ. de Saint-Etienne, Saint-Etienne, France"],"affiliations":[{"raw_affiliation_string":"Univ. de Saint-Etienne, Saint-Etienne, France","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107640533","display_name":"Fr\u00e9d\u00e9ric Rousseau","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Frederic Rousseau","raw_affiliation_strings":["TIMA Laboratory, Grenoble, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, Grenoble, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077146690","display_name":"Pascal R\u00e9my","orcid":"https://orcid.org/0000-0002-7305-9340"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Pascal Remy","raw_affiliation_strings":["ADACSYS, Courbevoie, France"],"affiliations":[{"raw_affiliation_string":"ADACSYS, Courbevoie, France","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5025896815"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.33346513,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.69773696,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"32","issue":null,"first_page":"61","last_page":"67"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8558270335197449},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7383366227149963},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7184097766876221},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5146173238754272},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.5085407495498657},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4878883361816406},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4797202944755554},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47586292028427124},{"id":"https://openalex.org/keywords/data-flow-analysis","display_name":"Data-flow analysis","score":0.46525460481643677},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.45540720224380493},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4289420247077942},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.41692647337913513}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8558270335197449},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7383366227149963},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7184097766876221},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5146173238754272},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.5085407495498657},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4878883361816406},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4797202944755554},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47586292028427124},{"id":"https://openalex.org/C88468194","wikidata":"https://www.wikidata.org/wiki/Q1172416","display_name":"Data-flow analysis","level":3,"score":0.46525460481643677},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.45540720224380493},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4289420247077942},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.41692647337913513},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/rsp.2015.7416548","is_oa":false,"landing_page_url":"http://doi.org/10.1109/rsp.2015.7416548","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Symposium on Rapid System Prototyping (RSP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6299999952316284,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1494930385","https://openalex.org/W1535550067","https://openalex.org/W1836639200","https://openalex.org/W1987800471","https://openalex.org/W2015458820","https://openalex.org/W2022673945","https://openalex.org/W2040832338","https://openalex.org/W2048706569","https://openalex.org/W2052550607","https://openalex.org/W2096044061","https://openalex.org/W2099474000","https://openalex.org/W2105664689","https://openalex.org/W2113615756","https://openalex.org/W2142483206","https://openalex.org/W2149935279","https://openalex.org/W2157095413","https://openalex.org/W2160642395","https://openalex.org/W2171318521","https://openalex.org/W2183824811","https://openalex.org/W4234381228","https://openalex.org/W4242125880","https://openalex.org/W6675417064","https://openalex.org/W6686078825","https://openalex.org/W6995434384"],"related_works":["https://openalex.org/W2269990635","https://openalex.org/W59945861","https://openalex.org/W2543290882","https://openalex.org/W2295153704","https://openalex.org/W3013057549","https://openalex.org/W1490270176","https://openalex.org/W1604320855","https://openalex.org/W1551967076","https://openalex.org/W1903431847","https://openalex.org/W1528221867"],"abstract_inverted_index":{"Network-on-Chip":[0],"(NoC)":[1],"is":[2,62,97],"an":[3,34],"interesting":[4],"communication":[5,47],"fabric":[6],"for":[7,76,124,137],"multi":[8],"processing":[9,91],"element":[10],"architectures":[11,116],"that":[12,23,80,117],"benefits":[13],"from":[14],"the":[15,31,42,50,87,94],"parallelism":[16,32],"of":[17,33,44,52,90,107],"algorithms.":[18],"We":[19,71],"present":[20],"a":[21,25,45,53,66,73,101],"method":[22,131],"uses":[24],"symbolic":[26],"execution":[27],"technique":[28],"to":[29,36,84,112],"extract":[30],"application":[35,59],"be":[37,119],"mapped":[38],"on":[39,86,121,132,140],"FPGAs":[40],"using":[41,65,108],"flexibility":[43],"NoC":[46],"infrastructure":[48],"and":[49,99],"properties":[51],"high":[54],"level":[55],"programming":[56],"language.":[57],"An":[58],"specific":[60],"hardware":[61],"then":[63],"generated":[64],"High":[67,125],"Level":[68],"Synthesis":[69],"flow.":[70],"provide":[72],"dedicated":[74],"mechanism":[75],"data":[77],"paths":[78],"reconfiguration":[79],"allows":[81],"different":[82],"applications":[83,135],"run":[85],"same":[88],"set":[89],"elements.":[92],"Thus,":[93],"output":[95],"design":[96,114],"programmable":[98],"has":[100],"processor-less":[102],"distributed":[103],"control.":[104],"This":[105],"approach":[106],"NoCs":[109],"enables":[110],"us":[111],"automatically":[113],"generic":[115],"can":[118],"used":[120,136],"FPGA":[122],"servers":[123],"Performance":[126],"Reconfigurable":[127],"Computing.We":[128],"validate":[129],"our":[130],"binomial":[133],"tree":[134],"option":[138],"pricing":[139],"FPGAs.":[141]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
