{"id":"https://openalex.org/W2113916958","doi":"https://doi.org/10.1109/rsp.2011.5929990","title":"A state-based modeling approach for fast performance evaluation of embedded system architectures","display_name":"A state-based modeling approach for fast performance evaluation of embedded system architectures","publication_year":2011,"publication_date":"2011-05-01","ids":{"openalex":"https://openalex.org/W2113916958","doi":"https://doi.org/10.1109/rsp.2011.5929990","mag":"2113916958"},"language":"en","primary_location":{"id":"doi:10.1109/rsp.2011.5929990","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp.2011.5929990","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 22nd IEEE International Symposium on Rapid System Prototyping","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044266294","display_name":"S\u00e9bastien Le Nours","orcid":"https://orcid.org/0000-0002-1562-7282"},"institutions":[{"id":"https://openalex.org/I97188460","display_name":"Nantes Universit\u00e9","ror":"https://ror.org/03gnr7b55","country_code":"FR","type":"education","lineage":["https://openalex.org/I97188460"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Sebastien Le Nours","raw_affiliation_strings":["IREENA, EA1770, Polytech-Nantes, University of Nantes, Nantes, France","Univ Nantes, IREENA, EA1770, Polytech-Nantes, rue C. Pauc, Nantes, F-44000 France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IREENA, EA1770, Polytech-Nantes, University of Nantes, Nantes, France","institution_ids":["https://openalex.org/I97188460"]},{"raw_affiliation_string":"Univ Nantes, IREENA, EA1770, Polytech-Nantes, rue C. Pauc, Nantes, F-44000 France","institution_ids":["https://openalex.org/I97188460"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111905376","display_name":"Anthony Barreteau","orcid":null},"institutions":[{"id":"https://openalex.org/I97188460","display_name":"Nantes Universit\u00e9","ror":"https://ror.org/03gnr7b55","country_code":"FR","type":"education","lineage":["https://openalex.org/I97188460"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Anthony Barreteau","raw_affiliation_strings":["IREENA, EA1770, Polytech-Nantes, University of Nantes, Nantes, France","Univ Nantes, IREENA, EA1770, Polytech-Nantes, rue C. Pauc, Nantes, F-44000 France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IREENA, EA1770, Polytech-Nantes, University of Nantes, Nantes, France","institution_ids":["https://openalex.org/I97188460"]},{"raw_affiliation_string":"Univ Nantes, IREENA, EA1770, Polytech-Nantes, rue C. Pauc, Nantes, F-44000 France","institution_ids":["https://openalex.org/I97188460"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109046560","display_name":"Olivier Pasquier","orcid":"https://orcid.org/0000-0002-7873-9732"},"institutions":[{"id":"https://openalex.org/I97188460","display_name":"Nantes Universit\u00e9","ror":"https://ror.org/03gnr7b55","country_code":"FR","type":"education","lineage":["https://openalex.org/I97188460"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Olivier Pasquier","raw_affiliation_strings":["IREENA, EA1770, Polytech-Nantes, University of Nantes, Nantes, France","Univ Nantes, IREENA, EA1770, Polytech-Nantes, rue C. Pauc, Nantes, F-44000 France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IREENA, EA1770, Polytech-Nantes, University of Nantes, Nantes, France","institution_ids":["https://openalex.org/I97188460"]},{"raw_affiliation_string":"Univ Nantes, IREENA, EA1770, Polytech-Nantes, rue C. Pauc, Nantes, F-44000 France","institution_ids":["https://openalex.org/I97188460"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.5153,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.68243741,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"8","issue":null,"first_page":"156","last_page":"162"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8124250173568726},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5806047320365906},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5660742521286011},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.5481675863265991},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4936426877975464},{"id":"https://openalex.org/keywords/state-space","display_name":"State space","score":0.4560624659061432},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4477340579032898},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.44702577590942383},{"id":"https://openalex.org/keywords/database-transaction","display_name":"Database transaction","score":0.44194090366363525},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4383653402328491},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43584734201431274},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.4266889989376068},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4159412682056427},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.41139650344848633},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.20331257581710815}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8124250173568726},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5806047320365906},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5660742521286011},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.5481675863265991},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4936426877975464},{"id":"https://openalex.org/C72434380","wikidata":"https://www.wikidata.org/wiki/Q230930","display_name":"State space","level":2,"score":0.4560624659061432},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4477340579032898},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.44702577590942383},{"id":"https://openalex.org/C75949130","wikidata":"https://www.wikidata.org/wiki/Q848010","display_name":"Database transaction","level":2,"score":0.44194090366363525},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4383653402328491},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43584734201431274},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4266889989376068},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4159412682056427},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.41139650344848633},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.20331257581710815},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/rsp.2011.5929990","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp.2011.5929990","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 22nd IEEE International Symposium on Rapid System Prototyping","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4000000059604645,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1495565530","https://openalex.org/W1536710422","https://openalex.org/W2040146928","https://openalex.org/W2045196269","https://openalex.org/W2053408517","https://openalex.org/W2054608565","https://openalex.org/W2063393378","https://openalex.org/W2074558871","https://openalex.org/W2076732255","https://openalex.org/W2097141385","https://openalex.org/W2102251825","https://openalex.org/W2120346621","https://openalex.org/W2126605998","https://openalex.org/W2141480229","https://openalex.org/W2151174323","https://openalex.org/W2155882166","https://openalex.org/W2481725867","https://openalex.org/W3150294762","https://openalex.org/W4229943461","https://openalex.org/W4231725471","https://openalex.org/W4238435901","https://openalex.org/W4249472430","https://openalex.org/W6682778044","https://openalex.org/W6820139873"],"related_works":["https://openalex.org/W2170029576","https://openalex.org/W2099940607","https://openalex.org/W2341647340","https://openalex.org/W2790192245","https://openalex.org/W2548514518","https://openalex.org/W2159507980","https://openalex.org/W1996984607","https://openalex.org/W1537885374","https://openalex.org/W3146054601","https://openalex.org/W2059569687"],"abstract_inverted_index":{"Abstract":[0],"models":[1,98],"are":[2,29,125],"means":[3],"to":[4,17,31,37,62,79,101],"assist":[5],"system":[6,34,123],"architects":[7],"in":[8],"the":[9,20,47,55,115],"evaluation":[10,42,64,119],"process":[11],"of":[12,24,46,57,65,68,82,87,94,110,114,120,122,129],"hardware/software":[13],"architectures":[14,35,124],"and":[15,36,43,99],"then":[16],"cope":[18],"with":[19],"still":[21,107],"increasing":[22],"complexity":[23],"embedded":[25,69],"systems.":[26,70],"Efficient":[27],"methods":[28],"necessary":[30],"correctly":[32],"model":[33],"make":[38],"possible":[39],"early":[40],"performance":[41],"fast":[44],"exploration":[45],"design":[48],"space.":[49],"In":[50],"this":[51],"paper,":[52],"we":[53],"present":[54],"use":[56],"a":[58,75],"specific":[59,131],"modeling":[60,81],"approach":[61,117],"improve":[63,80],"non-functional":[66],"properties":[67,83],"The":[71,112],"contribution":[72],"is":[73],"about":[74],"computation":[76],"method":[77,91],"defined":[78],"used":[84],"for":[85,118],"assessment":[86],"architecture":[88],"performances.":[89],"This":[90],"favors":[92],"creation":[93],"abstract":[95],"transaction":[96],"level":[97],"leads":[100],"significantly":[102],"reducing":[103],"simulation":[104],"time":[105],"but":[106],"preserving":[108],"accuracy":[109],"results.":[111],"benefits":[113],"proposed":[116],"performances":[121],"highlighted":[126],"through":[127],"analysis":[128],"two":[130],"case":[132],"studies.":[133]},"counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
