{"id":"https://openalex.org/W2168363137","doi":"https://doi.org/10.1109/rsp.2008.32","title":"Functional DIF for Rapid Prototyping","display_name":"Functional DIF for Rapid Prototyping","publication_year":2008,"publication_date":"2008-06-01","ids":{"openalex":"https://openalex.org/W2168363137","doi":"https://doi.org/10.1109/rsp.2008.32","mag":"2168363137"},"language":"en","primary_location":{"id":"doi:10.1109/rsp.2008.32","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp.2008.32","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060997298","display_name":"William Plishker","orcid":"https://orcid.org/0000-0001-6119-7415"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"William Plishker","raw_affiliation_strings":["Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies, University of Maryland, College Park, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies, University of Maryland, College Park, USA","institution_ids":["https://openalex.org/I66946132"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113854244","display_name":"Nimish Sane","orcid":null},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nimish Sane","raw_affiliation_strings":["Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies, University of Maryland, College Park, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies, University of Maryland, College Park, USA","institution_ids":["https://openalex.org/I66946132"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064709844","display_name":"Mary Kiemb","orcid":null},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mary Kiemb","raw_affiliation_strings":["Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies, University of Maryland, College Park, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies, University of Maryland, College Park, USA","institution_ids":["https://openalex.org/I66946132"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080319339","display_name":"Kapil Anand","orcid":null},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kapil Anand","raw_affiliation_strings":["Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies, University of Maryland, College Park, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies, University of Maryland, College Park, USA","institution_ids":["https://openalex.org/I66946132"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038036261","display_name":"Shuvra S. Bhattacharyya","orcid":"https://orcid.org/0000-0001-7719-1106"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shuvra S. Bhattacharyya","raw_affiliation_strings":["Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies, University of Maryland, College Park, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies, University of Maryland, College Park, USA","institution_ids":["https://openalex.org/I66946132"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5060997298"],"corresponding_institution_ids":["https://openalex.org/I66946132"],"apc_list":null,"apc_paid":null,"fwci":13.1711,"has_fulltext":false,"cited_by_count":101,"citation_normalized_percentile":{"value":0.98971642,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"1 4","issue":null,"first_page":"17","last_page":"23"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.9817007184028625},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.826388955116272},{"id":"https://openalex.org/keywords/dataflow-architecture","display_name":"Dataflow architecture","score":0.7506657838821411},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5656340718269348},{"id":"https://openalex.org/keywords/model-of-computation","display_name":"Model of computation","score":0.5643660426139832},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5247876048088074},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.43880587816238403},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3866806626319885},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.3513193428516388},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3430725932121277},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.31382912397384644}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.9817007184028625},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.826388955116272},{"id":"https://openalex.org/C176727019","wikidata":"https://www.wikidata.org/wiki/Q1172415","display_name":"Dataflow architecture","level":3,"score":0.7506657838821411},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5656340718269348},{"id":"https://openalex.org/C184596265","wikidata":"https://www.wikidata.org/wiki/Q2651576","display_name":"Model of computation","level":3,"score":0.5643660426139832},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5247876048088074},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.43880587816238403},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3866806626319885},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.3513193428516388},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3430725932121277},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.31382912397384644}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/rsp.2008.32","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rsp.2008.32","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4099999964237213}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306250","display_name":"Battelle","ror":"https://ror.org/01h5tnr73"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1534574783","https://openalex.org/W1556393540","https://openalex.org/W1860183717","https://openalex.org/W2033872646","https://openalex.org/W2038096666","https://openalex.org/W2054608565","https://openalex.org/W2061500932","https://openalex.org/W2091158003","https://openalex.org/W2104144645","https://openalex.org/W2104922219","https://openalex.org/W2110278976","https://openalex.org/W2113853451","https://openalex.org/W2115141746","https://openalex.org/W2120431055","https://openalex.org/W2122585865","https://openalex.org/W2135650100","https://openalex.org/W2166453943","https://openalex.org/W2169180789","https://openalex.org/W2179825846","https://openalex.org/W2538982244","https://openalex.org/W4229943461","https://openalex.org/W4234937091","https://openalex.org/W6631926835","https://openalex.org/W6658957694","https://openalex.org/W6684750625","https://openalex.org/W7017311319"],"related_works":["https://openalex.org/W2277357125","https://openalex.org/W4229975623","https://openalex.org/W2077180914","https://openalex.org/W2188794726","https://openalex.org/W2108674173","https://openalex.org/W1484403103","https://openalex.org/W1743410484","https://openalex.org/W2017802743","https://openalex.org/W1832272004","https://openalex.org/W1894511976"],"abstract_inverted_index":{"Dataflow":[0],"formalisms":[1],"have":[2],"provided":[3],"designers":[4,24],"of":[5,29,43,58,89,101,110,135],"digital":[6],"signal":[7],"processing":[8],"systems":[9],"with":[10],"optimizations":[11],"and":[12,52,66,98,114,128,173],"guarantees":[13],"to":[14,34,49,159,165],"arrive":[15,166],"at":[16,167,175],"quality":[17],"prototypes":[18],"quickly.":[19],"As":[20],"system":[21],"complexity":[22],"increases,":[23],"are":[25],"expressing":[26],"more":[27,180],"types":[28],"behavior":[30],"in":[31,64],"dataflow":[32,45,87,93,116,123],"languages":[33],"retain":[35],"these":[36],"implementation":[37],"benefits.":[38],"While":[39],"the":[40,76,107,122,130,133,162],"semantic":[41],"range":[42],"DSP-oriented":[44],"models":[46],"has":[47,61,68],"expanded":[48],"cover":[50],"quasi-static":[51],"dynamic":[53,113],"applications,":[54],"efficient":[55,99],"functional":[56,72,170,177],"simulation":[57,73,157,171],"such":[59],"applications":[60],"not.":[62],"Complexity":[63],"scheduling":[65],"modeling":[67],"impeded":[69],"efforts":[70],"towards":[71],"that":[74,95,147],"matches":[75],"final":[77],"implementation.":[78,143],"We":[79,118],"provide":[80],"this":[81],"functionality":[82],"by":[83],"introducing":[84],"a":[85,136,148,168,176],"new":[86],"model":[88],"computation,":[90],"called":[91],"enable-invoke":[92],"(EIDF),":[94],"supports":[96],"flexible":[97],"prototyping":[100],"dataflow-based":[102],"application":[103,163],"representations.":[104],"EIDF":[105,120,153],"permits":[106],"natural":[108],"description":[109],"actors":[111],"for":[112],"static":[115],"models.":[117],"integrate":[119],"into":[121],"interchange":[124],"format":[125],"(DIF)":[126],"package":[127],"demonstrate":[129],"approach":[131],"on":[132,152],"design":[134,149,184],"polynomial":[137],"evaluation":[138],"accelerator":[139],"targeting":[140],"an":[141],"FPGA":[142],"Our":[144],"experiments":[145],"show":[146],"environment":[150],"based":[151],"can":[154],"achieve":[155],"functionally-correct":[156],"compared":[158],"Verilog,":[160],"allowing":[161],"designer":[164],"verified":[169],"faster,":[172],"therefore":[174],"prototype":[178],"much":[179],"quickly":[181],"than":[182],"traditional":[183],"practices.":[185]},"counts_by_year":[{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":10},{"year":2016,"cited_by_count":9},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":7},{"year":2013,"cited_by_count":9},{"year":2012,"cited_by_count":7}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
