{"id":"https://openalex.org/W4416740371","doi":"https://doi.org/10.1109/rfid-ta63091.2025.11265914","title":"A Versatile and Easy-to-Use Python-Based EDA Tool for Analog and RF Schematic Level IC Design","display_name":"A Versatile and Easy-to-Use Python-Based EDA Tool for Analog and RF Schematic Level IC Design","publication_year":2025,"publication_date":"2025-10-28","ids":{"openalex":"https://openalex.org/W4416740371","doi":"https://doi.org/10.1109/rfid-ta63091.2025.11265914"},"language":null,"primary_location":{"id":"doi:10.1109/rfid-ta63091.2025.11265914","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rfid-ta63091.2025.11265914","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Conference on RFID Technology and Applications (RFID-TA)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5120617190","display_name":"Th\u00e9o Prats Rioufol","orcid":null},"institutions":[{"id":"https://openalex.org/I107428990","display_name":"Instituto Tecnol\u00f3gico de Aeron\u00e1utica","ror":"https://ror.org/05vh67662","country_code":"BR","type":"education","lineage":["https://openalex.org/I107428990"]},{"id":"https://openalex.org/I3019908861","display_name":"Laboratoire de G\u00e9nie \u00c9lectrique et \u00c9lectronique de Paris","ror":"https://ror.org/02xnnng09","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I277688954","https://openalex.org/I277688954","https://openalex.org/I3019908861","https://openalex.org/I39804081","https://openalex.org/I4210107720"]}],"countries":["BR","FR"],"is_corresponding":false,"raw_author_name":"Th\u00e9o Prats Rioufol","raw_affiliation_strings":["Aeronautics Institute of Technology - ITA,ITA Integrated Circuits Laboratory,S&#x00E3;o Jos&#x00E9; dos Campos,Brazil","ITA - Instituto Tecnol\u00f3gico de Aeron\u00e1utica =  Aeronautics Institute of Technology [Br\u00e9sil] (Pra\u00e7a Marechal Eduardo Gomes, 50 - Vila das Ac\u00e1cias CEP 12.228-900 S\u00e3o Jos\u00e9 dos Campos SP - Brazil)","GeePs - Laboratoire G\u00e9nie \u00e9lectrique et \u00e9lectronique de Paris (11, rue Joliot Curie\r\nPlateau de Moulon\r\n91192 Gif sur Yvette - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Aeronautics Institute of Technology - ITA,ITA Integrated Circuits Laboratory,S&#x00E3;o Jos&#x00E9; dos Campos,Brazil","institution_ids":["https://openalex.org/I107428990"]},{"raw_affiliation_string":"ITA - Instituto Tecnol\u00f3gico de Aeron\u00e1utica =  Aeronautics Institute of Technology [Br\u00e9sil] (Pra\u00e7a Marechal Eduardo Gomes, 50 - Vila das Ac\u00e1cias CEP 12.228-900 S\u00e3o Jos\u00e9 dos Campos SP - Brazil)","institution_ids":["https://openalex.org/I107428990"]},{"raw_affiliation_string":"GeePs - Laboratoire G\u00e9nie \u00e9lectrique et \u00e9lectronique de Paris (11, rue Joliot Curie\r\nPlateau de Moulon\r\n91192 Gif sur Yvette - France)","institution_ids":["https://openalex.org/I3019908861"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017282448","display_name":"Lucas Compassi-Severo","orcid":"https://orcid.org/0000-0002-3092-4023"},"institutions":[{"id":"https://openalex.org/I107428990","display_name":"Instituto Tecnol\u00f3gico de Aeron\u00e1utica","ror":"https://ror.org/05vh67662","country_code":"BR","type":"education","lineage":["https://openalex.org/I107428990"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Lucas Compassi-Severo","raw_affiliation_strings":["Aeronautics Institute of Technology - ITA,ITA Integrated Circuits Laboratory,S&#x00E3;o Jos&#x00E9; dos Campos,Brazil","ITA - Instituto Tecnol\u00f3gico de Aeron\u00e1utica =  Aeronautics Institute of Technology [Br\u00e9sil] (Pra\u00e7a Marechal Eduardo Gomes, 50 - Vila das Ac\u00e1cias CEP 12.228-900 S\u00e3o Jos\u00e9 dos Campos SP - Brazil)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Aeronautics Institute of Technology - ITA,ITA Integrated Circuits Laboratory,S&#x00E3;o Jos&#x00E9; dos Campos,Brazil","institution_ids":["https://openalex.org/I107428990"]},{"raw_affiliation_string":"ITA - Instituto Tecnol\u00f3gico de Aeron\u00e1utica =  Aeronautics Institute of Technology [Br\u00e9sil] (Pra\u00e7a Marechal Eduardo Gomes, 50 - Vila das Ac\u00e1cias CEP 12.228-900 S\u00e3o Jos\u00e9 dos Campos SP - Brazil)","institution_ids":["https://openalex.org/I107428990"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.4814000129699707,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.4814000129699707,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.18569999933242798,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.07280000299215317,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.7892000079154968},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.63919997215271},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.5551000237464905},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5371000170707703},{"id":"https://openalex.org/keywords/design-tool","display_name":"Design tool","score":0.5357000231742859},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5142999887466431},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4675000011920929},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.46389999985694885},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.45509999990463257}],"concepts":[{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.7892000079154968},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.63919997215271},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.5551000237464905},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5547000169754028},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5371000170707703},{"id":"https://openalex.org/C2777466363","wikidata":"https://www.wikidata.org/wiki/Q17008971","display_name":"Design tool","level":2,"score":0.5357000231742859},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5142999887466431},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4964999854564667},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4675000011920929},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.46389999985694885},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.45509999990463257},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.412200003862381},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.4083000123500824},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.3806999921798706},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.37130001187324524},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.33980000019073486},{"id":"https://openalex.org/C119823426","wikidata":"https://www.wikidata.org/wiki/Q184793","display_name":"Computer Aided Design","level":2,"score":0.3357999920845032},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.328900009393692},{"id":"https://openalex.org/C2778588580","wikidata":"https://www.wikidata.org/wiki/Q6043060","display_name":"Integrated design","level":2,"score":0.31869998574256897},{"id":"https://openalex.org/C188985296","wikidata":"https://www.wikidata.org/wiki/Q868954","display_name":"Page layout","level":2,"score":0.3005000054836273},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.298799991607666},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.2969000041484833},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.2838999927043915},{"id":"https://openalex.org/C34559072","wikidata":"https://www.wikidata.org/wiki/Q2334061","display_name":"Design of experiments","level":2,"score":0.28049999475479126},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.27559998631477356},{"id":"https://openalex.org/C2778096292","wikidata":"https://www.wikidata.org/wiki/Q1779650","display_name":"Design engineer","level":2,"score":0.2732999920845032},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2703999876976013},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.2583000063896179},{"id":"https://openalex.org/C34972735","wikidata":"https://www.wikidata.org/wiki/Q2920267","display_name":"Engineering design process","level":2,"score":0.25609999895095825},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2522999942302704},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.25099998712539673}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/rfid-ta63091.2025.11265914","is_oa":false,"landing_page_url":"https://doi.org/10.1109/rfid-ta63091.2025.11265914","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Conference on RFID Technology and Applications (RFID-TA)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W3046062028","https://openalex.org/W3160469020","https://openalex.org/W4389169617","https://openalex.org/W4390629676","https://openalex.org/W4403278664","https://openalex.org/W4404238974"],"related_works":[],"abstract_inverted_index":{"EDA":[0],"tools":[1,25,50,83],"are":[2,84],"required":[3],"by":[4,87],"analog":[5],"and":[6,19,35,133],"RF":[7,142],"designers":[8],"to":[9,21,43,63,135,143,163],"assist":[10],"the":[11,30,33,56,117,136,158,161],"circuit":[12],"sizing":[13],"stage,":[14],"thereby":[15],"reducing":[16],"work":[17,93],"effort":[18],"time":[20],"market.":[22],"Several":[23],"optimisation-based":[24],"have":[26],"been":[27],"proposed":[28,118,129],"in":[29,123,147],"literature":[31],"since":[32],"1980s,":[34],"their":[36,70],"use":[37,64],"has":[38],"presented":[39,132],"important":[40],"improvements":[41],"due":[42],"efficient":[44],"design":[45,76,137,154],"space":[46],"exploration.":[47],"However,":[48],"these":[49,82],"often":[51],"require":[52],"extended":[53],"knowledge":[54],"about":[55],"tool's":[57],"algorithm":[58],"implementation,":[59],"making":[60],"them":[61],"hard":[62],"for":[65,74],"IC":[66],"designers.":[67,88],"Precisely":[68],"controlling":[69],"configuration":[71],"is":[72,131],"mandatory":[73],"good":[75],"flow":[77],"tuning.":[78],"As":[79],"a":[80,95,107,113,139,148],"result,":[81],"not":[85],"well-received":[86],"In":[89],"this":[90,92],"way,":[91],"proposes":[94],"Python-based":[96],"optimization":[97],"tool":[98,119,130,162],"that":[99],"presents":[100],"an":[101],"Easy-to-Use":[102],"user":[103],"interface,":[104],"integrated":[105],"with":[106],"widely":[108],"available":[109],"commercial":[110],"EDA.":[111],"With":[112],"simplified":[114],"three-step":[115],"setup,":[116],"can":[120],"be":[121],"configured":[122],"less":[124],"than":[125],"2":[126],"minutes.":[127],"The":[128],"applied":[134],"of":[138,160],"915":[140],"MHz":[141],"DC":[144],"converter":[145],"implemented":[146],"CMOS":[149],"65":[150],"nm":[151],"process.":[152],"Different":[153],"optimisation":[155],"scenarios":[156],"illustrate":[157],"flexibility":[159],"requirements.":[164]},"counts_by_year":[],"updated_date":"2026-07-23T08:03:31.855105","created_date":"2025-11-28T00:00:00"}
