{"id":"https://openalex.org/W1526946326","doi":"https://doi.org/10.1109/retis.2015.7232927","title":"Implementation of 4-bit carry select adder using Diode free adiabatic logic (DFAL)","display_name":"Implementation of 4-bit carry select adder using Diode free adiabatic logic (DFAL)","publication_year":2015,"publication_date":"2015-07-01","ids":{"openalex":"https://openalex.org/W1526946326","doi":"https://doi.org/10.1109/retis.2015.7232927","mag":"1526946326"},"language":"en","primary_location":{"id":"doi:10.1109/retis.2015.7232927","is_oa":false,"landing_page_url":"https://doi.org/10.1109/retis.2015.7232927","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049980654","display_name":"Sanjay Singh","orcid":"https://orcid.org/0009-0004-0226-5384"},"institutions":[{"id":"https://openalex.org/I49702814","display_name":"Mewar University","ror":"https://ror.org/01qva9798","country_code":"IN","type":"education","lineage":["https://openalex.org/I49702814"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Sanjay Singh","raw_affiliation_strings":["Electronics and Communication Engineering Department, MEWAR UNIVERSITY, Chittorgarh, RAJASTHAN, INDIA","Electronics and Communication Engineering Department, MEWAR UNIVERSITY, Chittorgarh, RAJASTHAN, India"],"affiliations":[{"raw_affiliation_string":"Electronics and Communication Engineering Department, MEWAR UNIVERSITY, Chittorgarh, RAJASTHAN, INDIA","institution_ids":["https://openalex.org/I49702814"]},{"raw_affiliation_string":"Electronics and Communication Engineering Department, MEWAR UNIVERSITY, Chittorgarh, RAJASTHAN, India","institution_ids":["https://openalex.org/I49702814"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054858388","display_name":"K. Srinivasa Rao","orcid":"https://orcid.org/0000-0003-1239-5196"},"institutions":[{"id":"https://openalex.org/I49702814","display_name":"Mewar University","ror":"https://ror.org/01qva9798","country_code":"IN","type":"education","lineage":["https://openalex.org/I49702814"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"K. Srinivasarao","raw_affiliation_strings":["Electronics and Communication Engineering Department, MEWAR UNIVERSITY, Chittorgarh, RAJASTHAN, INDIA","Electronics and Communication Engineering Department, MEWAR UNIVERSITY, Chittorgarh, RAJASTHAN, India"],"affiliations":[{"raw_affiliation_string":"Electronics and Communication Engineering Department, MEWAR UNIVERSITY, Chittorgarh, RAJASTHAN, INDIA","institution_ids":["https://openalex.org/I49702814"]},{"raw_affiliation_string":"Electronics and Communication Engineering Department, MEWAR UNIVERSITY, Chittorgarh, RAJASTHAN, India","institution_ids":["https://openalex.org/I49702814"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5049980654"],"corresponding_institution_ids":["https://openalex.org/I49702814"],"apc_list":null,"apc_paid":null,"fwci":0.3946,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.64915453,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"2013","issue":null,"first_page":"481","last_page":"484"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9004131555557251},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6045929193496704},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5958917140960693},{"id":"https://openalex.org/keywords/adiabatic-circuit","display_name":"Adiabatic circuit","score":0.566595196723938},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5352011322975159},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5293508172035217},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5023186206817627},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.5014505386352539},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.49507656693458557},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.49129408597946167},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.47766146063804626},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.45759376883506775},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.45662957429885864},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.44916728138923645},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.34649035334587097},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3263165354728699},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.29421576857566833},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21967586874961853},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.0967758297920227}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9004131555557251},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6045929193496704},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5958917140960693},{"id":"https://openalex.org/C87606752","wikidata":"https://www.wikidata.org/wiki/Q4682637","display_name":"Adiabatic circuit","level":5,"score":0.566595196723938},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5352011322975159},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5293508172035217},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5023186206817627},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.5014505386352539},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.49507656693458557},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.49129408597946167},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.47766146063804626},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.45759376883506775},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.45662957429885864},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.44916728138923645},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.34649035334587097},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3263165354728699},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.29421576857566833},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21967586874961853},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.0967758297920227}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/retis.2015.7232927","is_oa":false,"landing_page_url":"https://doi.org/10.1109/retis.2015.7232927","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7900000214576721,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1971467632","https://openalex.org/W1976039195","https://openalex.org/W2042121042","https://openalex.org/W2122377402","https://openalex.org/W2129142934","https://openalex.org/W2162211138","https://openalex.org/W2533651815","https://openalex.org/W6660935213"],"related_works":["https://openalex.org/W2777618078","https://openalex.org/W2289213137","https://openalex.org/W2902180427","https://openalex.org/W2186469553","https://openalex.org/W2997250644","https://openalex.org/W2339546864","https://openalex.org/W2181740462","https://openalex.org/W1108467054","https://openalex.org/W4308329128","https://openalex.org/W4384928667"],"abstract_inverted_index":{"Adiabatic":[0],"Logic":[1],"is":[2,8,59,79,90],"the":[3,137],"most":[4],"effective":[5],"technique":[6,126],"which":[7,40],"used":[9,104],"for":[10,50,117],"implementing":[11],"of":[12,67,76,133,141],"low":[13,24,51],"power":[14,25,52,130],"digital":[15,56],"logic":[16,38,135],"circuits.":[17],"In":[18,55,98],"this":[19,99],"research":[20,100],"paper":[21,101],"to":[22],"designed":[23],"Dissipation":[26],"carry":[27],"select":[28,86],"adder":[29,43,58,78],"using":[30,84],"DFAL":[31],"2X1":[32],"mux":[33],"and":[34,113],"Diode":[35,123],"free":[36,124],"adiabatic":[37,125],"(DFAL)":[39],"compare":[41],"proposed":[42],"circuit":[44],"with":[45,95,110,136],"CMOS":[46,116,134],"Technology":[47],"Designed":[48],"Adder":[49],"VLSI":[53],"Application.":[54],"electronics,":[57],"a":[60,71],"play":[61],"important":[62],"role":[63],"that":[64,122],"performs":[65],"addition":[66],"binary":[68],"numbers.":[69],"Now":[70],"days":[72],"The":[73],"Propagation":[74],"Delay":[75],"Each":[77],"major":[80],"problem":[81],"overcomes":[82],"by":[83],"Carry":[85],"Adder.":[87],"Its":[88],"area":[89],"slightly":[91],"increasing":[92],"as":[93],"compared":[94],"normal":[96],"adder.":[97],"we":[102],"have":[103,120],"T_SPICE":[105],"simulator":[106],"at":[107],"0.18\u03bcm":[108],"technology":[109],"Mosis":[111],"Modal":[112],"1.8V":[114],"standard":[115],"simulation.":[118],"We":[119],"observed":[121],"saves":[127],"55%":[128],"more":[129],"in":[131],"comparison":[132],"transition":[138],"frequency":[139],"range":[140],"10-80MHZ.":[142]},"counts_by_year":[{"year":2017,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}