{"id":"https://openalex.org/W2888925416","doi":"https://doi.org/10.1109/recosoc.2018.8449388","title":"An Integrated Toolchain for Overlay-centric System-on-chip","display_name":"An Integrated Toolchain for Overlay-centric System-on-chip","publication_year":2018,"publication_date":"2018-07-01","ids":{"openalex":"https://openalex.org/W2888925416","doi":"https://doi.org/10.1109/recosoc.2018.8449388","mag":"2888925416"},"language":"en","primary_location":{"id":"doi:10.1109/recosoc.2018.8449388","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2018.8449388","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049336540","display_name":"Jean-Christophe Le Lann","orcid":"https://orcid.org/0000-0003-2555-1805"},"institutions":[{"id":"https://openalex.org/I4210148559","display_name":"\u00c9cole nationale sup\u00e9rieure de techniques avanc\u00e9es Bretagne","ror":"https://ror.org/059n54003","country_code":"FR","type":"education","lineage":["https://openalex.org/I201181511","https://openalex.org/I4210145102","https://openalex.org/I4210148559"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Jean-Christophe Le Lann","raw_affiliation_strings":["ENSTA Bretagne and Lab-STICC UMR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENSTA Bretagne and Lab-STICC UMR","institution_ids":["https://openalex.org/I4210148559"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048077564","display_name":"Th\u00e9otime Bollengier","orcid":"https://orcid.org/0009-0006-7315-2736"},"institutions":[{"id":"https://openalex.org/I4210148559","display_name":"\u00c9cole nationale sup\u00e9rieure de techniques avanc\u00e9es Bretagne","ror":"https://ror.org/059n54003","country_code":"FR","type":"education","lineage":["https://openalex.org/I201181511","https://openalex.org/I4210145102","https://openalex.org/I4210148559"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Theotime Bollengier","raw_affiliation_strings":["ENSTA Bretagne and Lab-STICC UMR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENSTA Bretagne and Lab-STICC UMR","institution_ids":["https://openalex.org/I4210148559"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041208504","display_name":"Mohamad Najem","orcid":"https://orcid.org/0000-0002-8729-4915"},"institutions":[{"id":"https://openalex.org/I4210148559","display_name":"\u00c9cole nationale sup\u00e9rieure de techniques avanc\u00e9es Bretagne","ror":"https://ror.org/059n54003","country_code":"FR","type":"education","lineage":["https://openalex.org/I201181511","https://openalex.org/I4210145102","https://openalex.org/I4210148559"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Mohamad Najem","raw_affiliation_strings":["ENSTA Bretagne and Lab-STICC UMR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENSTA Bretagne and Lab-STICC UMR","institution_ids":["https://openalex.org/I4210148559"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061188155","display_name":"Lo\u00efc Lagadec","orcid":"https://orcid.org/0000-0003-3778-3144"},"institutions":[{"id":"https://openalex.org/I4210148559","display_name":"\u00c9cole nationale sup\u00e9rieure de techniques avanc\u00e9es Bretagne","ror":"https://ror.org/059n54003","country_code":"FR","type":"education","lineage":["https://openalex.org/I201181511","https://openalex.org/I4210145102","https://openalex.org/I4210148559"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Loic Lagadec","raw_affiliation_strings":["ENSTA Bretagne and Lab-STICC UMR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENSTA Bretagne and Lab-STICC UMR","institution_ids":["https://openalex.org/I4210148559"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210148559"],"apc_list":null,"apc_paid":null,"fwci":0.2305,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.51387038,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"2147","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.8603689670562744},{"id":"https://openalex.org/keywords/toolchain","display_name":"Toolchain","score":0.8505953550338745},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7821478247642517},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7819146513938904},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7259376645088196},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6921120285987854},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.614416778087616},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5595812797546387},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5423804521560669},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5116384625434875},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4464970827102661},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4116639494895935},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.26469069719314575},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.11856606602668762},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.08967742323875427}],"concepts":[{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.8603689670562744},{"id":"https://openalex.org/C2777062904","wikidata":"https://www.wikidata.org/wiki/Q545406","display_name":"Toolchain","level":3,"score":0.8505953550338745},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7821478247642517},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7819146513938904},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7259376645088196},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6921120285987854},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.614416778087616},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5595812797546387},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5423804521560669},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5116384625434875},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4464970827102661},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4116639494895935},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.26469069719314575},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.11856606602668762},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.08967742323875427},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/recosoc.2018.8449388","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2018.8449388","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-01867638v1","is_oa":false,"landing_page_url":"https://ensta.hal.science/hal-01867638","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.univ-valenciennes.fr/evenements/recosoc","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.49000000953674316,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1497161204","https://openalex.org/W1528837436","https://openalex.org/W1554938446","https://openalex.org/W1967139892","https://openalex.org/W1969529818","https://openalex.org/W1972387588","https://openalex.org/W2014316444","https://openalex.org/W2091720183","https://openalex.org/W2107350738","https://openalex.org/W2112357703","https://openalex.org/W2139637699","https://openalex.org/W2150022482","https://openalex.org/W2168493238","https://openalex.org/W2411785910","https://openalex.org/W2554510265","https://openalex.org/W2586912292","https://openalex.org/W2592947564","https://openalex.org/W2775414535","https://openalex.org/W4206664135","https://openalex.org/W4252552852","https://openalex.org/W6629768150","https://openalex.org/W6746867433"],"related_works":["https://openalex.org/W2912406603","https://openalex.org/W2045545092","https://openalex.org/W2276389599","https://openalex.org/W1595273177","https://openalex.org/W2388040150","https://openalex.org/W4200122249","https://openalex.org/W4230718388","https://openalex.org/W2002682434","https://openalex.org/W2102117846","https://openalex.org/W2481546399"],"abstract_inverted_index":{"The":[0],"overlay":[1,67],"approach":[2],"-FPGA":[3],"over":[4],"FPGA-":[5],"has":[6],"a":[7,51],"number":[8,30],"of":[9,26,31,41],"expected":[10],"benefits,":[11],"including":[12],"bitstream":[13],"compatibility":[14],"between":[15],"different":[16],"vendors":[17],"and":[18,38,63],"parts,":[19],"fast":[20],"reconfiguration":[21],"and,":[22],"more":[23],"generally,":[24],"ease":[25],"use.":[27],"However":[28],"the":[29,65],"complex":[32],"engineering":[33],"tasks":[34],"to":[35],"design,":[36],"explore":[37],"make":[39],"use":[40],"such":[42],"overlays":[43],"severely":[44],"restrains":[45],"their":[46],"diffusion.":[47],"This":[48],"paper":[49],"presents":[50],"downloadable":[52],"integrated":[53],"tool":[54],"flow":[55],"named":[56],"Argen.":[57],"Argen":[58],"supports":[59],"defining":[60],"reconfigurable":[61],"architecture":[62],"generating":[64],"corresponding":[66],"along":[68],"with":[69],"its":[70],"System-on-chip":[71],"exploitation":[72],"environment.":[73]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-07-02T09:51:11.867554","created_date":"2025-10-10T00:00:00"}