{"id":"https://openalex.org/W2746098685","doi":"https://doi.org/10.1109/recosoc.2017.8016159","title":"Programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm","display_name":"Programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm","publication_year":2017,"publication_date":"2017-07-01","ids":{"openalex":"https://openalex.org/W2746098685","doi":"https://doi.org/10.1109/recosoc.2017.8016159","mag":"2746098685"},"language":"en","primary_location":{"id":"doi:10.1109/recosoc.2017.8016159","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2017.8016159","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010926146","display_name":"Adrian Dominguez","orcid":null},"institutions":[{"id":"https://openalex.org/I119635470","display_name":"Universidad de Las Palmas de Gran Canaria","ror":"https://ror.org/01teme464","country_code":"ES","type":"education","lineage":["https://openalex.org/I119635470"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Adrian Dominguez","raw_affiliation_strings":["Institute for Applied Microelectronics, University of de Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain"],"affiliations":[{"raw_affiliation_string":"Institute for Applied Microelectronics, University of de Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain","institution_ids":["https://openalex.org/I119635470"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033099381","display_name":"Pedro P. Carballo","orcid":"https://orcid.org/0000-0001-7912-8768"},"institutions":[{"id":"https://openalex.org/I119635470","display_name":"Universidad de Las Palmas de Gran Canaria","ror":"https://ror.org/01teme464","country_code":"ES","type":"education","lineage":["https://openalex.org/I119635470"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pedro P. Carballo","raw_affiliation_strings":["Institute for Applied Microelectronics, University of de Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain"],"affiliations":[{"raw_affiliation_string":"Institute for Applied Microelectronics, University of de Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain","institution_ids":["https://openalex.org/I119635470"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5015901595","display_name":"Antonio N\u00fa\u00f1ez","orcid":"https://orcid.org/0000-0003-1295-1594"},"institutions":[{"id":"https://openalex.org/I119635470","display_name":"Universidad de Las Palmas de Gran Canaria","ror":"https://ror.org/01teme464","country_code":"ES","type":"education","lineage":["https://openalex.org/I119635470"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Antonio Nunez","raw_affiliation_strings":["Institute for Applied Microelectronics, University of de Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain"],"affiliations":[{"raw_affiliation_string":"Institute for Applied Microelectronics, University of de Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain","institution_ids":["https://openalex.org/I119635470"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5010926146"],"corresponding_institution_ids":["https://openalex.org/I119635470"],"apc_list":null,"apc_paid":null,"fwci":1.8025,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.86593642,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"5","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9897000193595886,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7991976737976074},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6879822015762329},{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.6756377220153809},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.5420554280281067},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5326176881790161},{"id":"https://openalex.org/keywords/deep-packet-inspection","display_name":"Deep packet inspection","score":0.49470922350883484},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4920899271965027},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4313357472419739},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.42683738470077515},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.401752233505249},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37476009130477905},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32505881786346436},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16825494170188904},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09752720594406128},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.0848478376865387}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7991976737976074},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6879822015762329},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.6756377220153809},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.5420554280281067},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5326176881790161},{"id":"https://openalex.org/C204679922","wikidata":"https://www.wikidata.org/wiki/Q734252","display_name":"Deep packet inspection","level":3,"score":0.49470922350883484},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4920899271965027},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4313357472419739},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.42683738470077515},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.401752233505249},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37476009130477905},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32505881786346436},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16825494170188904},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09752720594406128},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0848478376865387}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/recosoc.2017.8016159","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2017.8016159","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5699999928474426,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1921854729","https://openalex.org/W1983788629","https://openalex.org/W2042265653","https://openalex.org/W2046215248","https://openalex.org/W2100621516","https://openalex.org/W2120286362","https://openalex.org/W2134826720","https://openalex.org/W2170862365","https://openalex.org/W2188922879","https://openalex.org/W2393727648","https://openalex.org/W2499369548","https://openalex.org/W2547998102","https://openalex.org/W2579773951","https://openalex.org/W2605373900","https://openalex.org/W6687424872"],"related_works":["https://openalex.org/W2037547261","https://openalex.org/W2534771569","https://openalex.org/W4311812695","https://openalex.org/W2117788426","https://openalex.org/W3011583392","https://openalex.org/W2291920536","https://openalex.org/W4226031521","https://openalex.org/W3160314615","https://openalex.org/W2381288267","https://openalex.org/W2155469080"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"the":[3,47,65,88,107,112],"work":[4],"done":[5],"to":[6,92,105,109],"design":[7,100],"a":[8,30,41,58],"SoC":[9,34],"platform":[10,26,66,83,98],"for":[11,19],"real-time":[12],"on-line":[13],"pattern":[14,42],"search":[15,43],"in":[16],"TCP":[17],"packets":[18],"Deep":[20],"Packet":[21],"Inspection":[22],"(DPI)":[23],"applications.":[24],"The":[25,82],"is":[27,84],"based":[28,99],"on":[29],"Xilinx":[31],"Zynq":[32],"programmable":[33],"and":[35,53,74,97],"includes":[36],"an":[37],"accelerator":[38],"that":[39,45,56],"implements":[40,67],"engine":[44],"extends":[46],"original":[48],"Boyer-Moore":[49],"algorithm":[50],"with":[51],"timing":[52],"logical":[54],"rules,":[55],"produces":[57],"very":[59],"complex":[60],"set":[61],"of":[62,70,87,111],"rules.":[63],"Also,":[64],"different":[68],"modes":[69],"operation,":[71],"including":[72],"SIMD":[73],"MISD":[75],"parallelism,":[76],"which":[77],"can":[78],"be":[79],"configured":[80],"on-line.":[81],"scalable":[85],"depending":[86],"analysis":[89],"requirement":[90],"up":[91],"8":[93],"Gbps.":[94],"High-Level":[95],"synthesis":[96],"methodologies":[101],"have":[102],"been":[103],"used":[104],"reduce":[106],"time":[108],"market":[110],"completed":[113],"system.":[114]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}