{"id":"https://openalex.org/W1480161407","doi":"https://doi.org/10.1109/recosoc.2015.7238092","title":"Hardware-accelerated Response Time Analysis for priority-preemptive Networks-on-Chip","display_name":"Hardware-accelerated Response Time Analysis for priority-preemptive Networks-on-Chip","publication_year":2015,"publication_date":"2015-06-01","ids":{"openalex":"https://openalex.org/W1480161407","doi":"https://doi.org/10.1109/recosoc.2015.7238092","mag":"1480161407"},"language":"en","primary_location":{"id":"doi:10.1109/recosoc.2015.7238092","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2015.7238092","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100935900","display_name":"MA Yun-feng","orcid":null},"institutions":[{"id":"https://openalex.org/I52099693","display_name":"University of York","ror":"https://ror.org/04m01e293","country_code":"GB","type":"education","lineage":["https://openalex.org/I52099693"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Yunfeng Ma","raw_affiliation_strings":["Department of Computer Science, University of York","Dept. of Comput. Sci., Univ. of York, UK"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of York","institution_ids":["https://openalex.org/I52099693"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Univ. of York, UK","institution_ids":["https://openalex.org/I52099693"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020591718","display_name":"Leandro Soares Indrusiak","orcid":"https://orcid.org/0000-0002-9938-2920"},"institutions":[{"id":"https://openalex.org/I52099693","display_name":"University of York","ror":"https://ror.org/04m01e293","country_code":"GB","type":"education","lineage":["https://openalex.org/I52099693"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Leandro Soares Indrusiak","raw_affiliation_strings":["Department of Computer Science, University of York","Dept. of Comput. Sci., Univ. of York, UK"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of York","institution_ids":["https://openalex.org/I52099693"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Univ. of York, UK","institution_ids":["https://openalex.org/I52099693"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5100935900"],"corresponding_institution_ids":["https://openalex.org/I52099693"],"apc_list":null,"apc_paid":null,"fwci":0.646,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.66558529,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9902999997138977,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7901254296302795},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5450671911239624},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.5395137667655945},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5307604670524597},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.5168155431747437},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5104919672012329},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5072943568229675},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.49030402302742004},{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.4826979637145996},{"id":"https://openalex.org/keywords/response-time","display_name":"Response time","score":0.4697207510471344},{"id":"https://openalex.org/keywords/execution-time","display_name":"Execution time","score":0.46269306540489197},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4603675603866577},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.45672115683555603},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4455625116825104},{"id":"https://openalex.org/keywords/preemption","display_name":"Preemption","score":0.4360637962818146},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4161231517791748},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.4156498610973358},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.41150206327438354},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3008633255958557},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10157352685928345},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10081103444099426},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09934091567993164}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7901254296302795},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5450671911239624},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.5395137667655945},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5307604670524597},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.5168155431747437},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5104919672012329},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5072943568229675},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.49030402302742004},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.4826979637145996},{"id":"https://openalex.org/C19012869","wikidata":"https://www.wikidata.org/wiki/Q578372","display_name":"Response time","level":2,"score":0.4697207510471344},{"id":"https://openalex.org/C2989134064","wikidata":"https://www.wikidata.org/wiki/Q288510","display_name":"Execution time","level":2,"score":0.46269306540489197},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4603675603866577},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.45672115683555603},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4455625116825104},{"id":"https://openalex.org/C206952183","wikidata":"https://www.wikidata.org/wiki/Q1193100","display_name":"Preemption","level":2,"score":0.4360637962818146},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4161231517791748},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.4156498610973358},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.41150206327438354},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3008633255958557},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10157352685928345},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10081103444099426},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09934091567993164},{"id":"https://openalex.org/C74650414","wikidata":"https://www.wikidata.org/wiki/Q11397","display_name":"Classical mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/recosoc.2015.7238092","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2015.7238092","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1574396483","https://openalex.org/W2010551507","https://openalex.org/W2022098216","https://openalex.org/W2042979415","https://openalex.org/W2043254158","https://openalex.org/W2091518118","https://openalex.org/W2109488193","https://openalex.org/W2153421159","https://openalex.org/W2164164042","https://openalex.org/W2169731778","https://openalex.org/W2262960161","https://openalex.org/W2530718516","https://openalex.org/W2537451884","https://openalex.org/W6684958486","https://openalex.org/W6728710170"],"related_works":["https://openalex.org/W1500315091","https://openalex.org/W2373738034","https://openalex.org/W1496327843","https://openalex.org/W1572184288","https://openalex.org/W1543783659","https://openalex.org/W136631479","https://openalex.org/W2156929691","https://openalex.org/W1549916137","https://openalex.org/W2383649123","https://openalex.org/W2390473631"],"abstract_inverted_index":{"End-to-End":[0],"Response":[1],"Time":[2],"Analysis":[3],"(E2ERTA)":[4],"can":[5],"be":[6],"used":[7],"to":[8,51],"examine":[9],"the":[10,24,28,35,53,58,61,69,72,82,88],"timing":[11,83],"performance":[12,59],"of":[13,19,26,34,43,60,90],"a":[14,40,77,93],"Network-on-Chip":[15],"(NoC).":[16],"The":[17,74],"complexity":[18],"its":[20,66],"calculation":[21],"increases":[22],"with":[23,46],"scaling":[25],"both":[27],"task":[29],"set":[30],"and":[31,64,95,102],"core":[32],"count":[33],"NoC.":[36],"This":[37],"paper":[38],"presents":[39],"hardware":[41],"implementation":[42],"E2ERTA":[44,91],"along":[45],"two":[47],"other":[48],"acceleration":[49],"schemes":[50],"reduce":[52],"computation":[54],"time.":[55],"We":[56],"explore":[57],"proposed":[62],"approach,":[63],"analyse":[65],"effectiveness":[67],"against":[68],"state-of-the-art":[70],"in":[71,80],"field.":[73],"results":[75],"show":[76],"significant":[78],"improvement":[79],"analysing":[81],"performance,":[84],"thus":[85],"potentially":[86],"enabling":[87],"use":[89],"as":[92],"fast":[94],"guaranteed":[96],"deterministic":[97],"admission":[98],"controller":[99],"for":[100],"open":[101],"dynamic":[103],"real-time":[104],"systems.":[105]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}