{"id":"https://openalex.org/W2056313687","doi":"https://doi.org/10.1109/recosoc.2014.6861353","title":"Leveraging partial dynamic reconfiguration on Zynq SoC FPGAs","display_name":"Leveraging partial dynamic reconfiguration on Zynq SoC FPGAs","publication_year":2014,"publication_date":"2014-05-01","ids":{"openalex":"https://openalex.org/W2056313687","doi":"https://doi.org/10.1109/recosoc.2014.6861353","mag":"2056313687"},"language":"en","primary_location":{"id":"doi:10.1109/recosoc.2014.6861353","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2014.6861353","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023189184","display_name":"Jaime Correa Rodriguez","orcid":null},"institutions":[{"id":"https://openalex.org/I177802217","display_name":"University of Mannheim","ror":"https://ror.org/031bsb921","country_code":"DE","type":"education","lineage":["https://openalex.org/I177802217"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Jaime Correa Rodriguez","raw_affiliation_strings":["Hochschule Mannheim, Mannheim, Baden-W\u00c3\u00bcrttemberg, DE","Dept. of Inf. Technol., Mannheim Univ. of Appl. Sci., Mannheim, Germany"],"affiliations":[{"raw_affiliation_string":"Hochschule Mannheim, Mannheim, Baden-W\u00c3\u00bcrttemberg, DE","institution_ids":[]},{"raw_affiliation_string":"Dept. of Inf. Technol., Mannheim Univ. of Appl. Sci., Mannheim, Germany","institution_ids":["https://openalex.org/I177802217"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087787574","display_name":"Kurt Ackermann","orcid":"https://orcid.org/0009-0005-8540-9263"},"institutions":[{"id":"https://openalex.org/I177802217","display_name":"University of Mannheim","ror":"https://ror.org/031bsb921","country_code":"DE","type":"education","lineage":["https://openalex.org/I177802217"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Kurt Franz Ackermann","raw_affiliation_strings":["Hochschule Mannheim, Mannheim, Baden-W\u00c3\u00bcrttemberg, DE","Dept. of Inf. Technol., Mannheim Univ. of Appl. Sci., Mannheim, Germany"],"affiliations":[{"raw_affiliation_string":"Hochschule Mannheim, Mannheim, Baden-W\u00c3\u00bcrttemberg, DE","institution_ids":[]},{"raw_affiliation_string":"Dept. of Inf. Technol., Mannheim Univ. of Appl. Sci., Mannheim, Germany","institution_ids":["https://openalex.org/I177802217"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5023189184"],"corresponding_institution_ids":["https://openalex.org/I177802217"],"apc_list":null,"apc_paid":null,"fwci":1.5324,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.82818875,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8521305322647095},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7397418022155762},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6464532613754272},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.624438464641571},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5636709332466125},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3683246970176697}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8521305322647095},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7397418022155762},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6464532613754272},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.624438464641571},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5636709332466125},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3683246970176697}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/recosoc.2014.6861353","is_oa":false,"landing_page_url":"https://doi.org/10.1109/recosoc.2014.6861353","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5699999928474426}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1531086201","https://openalex.org/W1983942558","https://openalex.org/W2130193491","https://openalex.org/W2134382506","https://openalex.org/W2146609198","https://openalex.org/W2158008050","https://openalex.org/W2163167297","https://openalex.org/W6631786729","https://openalex.org/W6681628427"],"related_works":["https://openalex.org/W2808484818","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2340647897","https://openalex.org/W4249632163","https://openalex.org/W2797161794","https://openalex.org/W2096938998","https://openalex.org/W1760305469","https://openalex.org/W2103526090","https://openalex.org/W1574948540"],"abstract_inverted_index":{"The":[0],"ability":[1],"of":[2,9,43,52,56,64,91,103],"modern":[3,22],"FPGAs":[4,23],"to":[5,25,67],"change":[6],"isolated":[7],"regions":[8],"their":[10,65],"configuration":[11,83],"during":[12,69,100],"run-time":[13],"is":[14],"increasingly":[15],"appreciated":[16],"by":[17],"industry.":[18],"Integrating":[19],"powerful":[20],"microprocessors":[21],"evolved":[24],"efficient":[26],"SoC":[27,59],"architectures,":[28],"making":[29],"dynamic":[30],"partial":[31],"reconfiguration":[32],"accessible":[33],"in":[34,62],"various":[35],"ways.":[36],"Nonetheless,":[37],"exploiting":[38],"this":[39,104],"technology":[40],"requires":[41],"minimization":[42],"the":[44,53,92,101],"implied":[45],"latency-overhead.":[46],"This":[47],"paper":[48],"offers":[49],"an":[50,89],"exploration":[51],"latest":[54,93],"generation":[55],"Xilinx":[57],"all-programmable":[58],"Zynq":[60],"devices":[61],"terms":[63],"capabilities":[66],"reconfigure":[68],"run-time.":[70],"Suitable":[71],"architectures":[72],"are":[73,78,106],"provided":[74],"and":[75,86],"performance":[76],"evaluations":[77],"given":[79],"for":[80],"both":[81],"internal":[82],"interfaces:":[84],"PCAP":[85],"ICAPE2.":[87],"Moreover,":[88],"analysis":[90],"tool-chain":[94],"as":[95,97],"well":[96],"roadblocks":[98],"encountered":[99],"progress":[102],"work":[105],"presented.":[107]},"counts_by_year":[{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
